ADP1048DC1-EVALZ Analog Devices, ADP1048DC1-EVALZ Datasheet - Page 80

• Manufacturer Part Number: ADP1048DC1-EVALZ
• Description: Daughter Cards & OEM Boards ADP1048 DAUGHTERCARD
• Manufacturer: Analog Devices
• Series: ADP1048r

Specifications of ADP1048DC1-EVALZ

• Rohs: yes
• Product: Daughter Cards
• Description/function: 100 kHz daughter board
• Dimensions: 40 mm x 25 mm
• Interface Type: I2C
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 3.3 V
• Factory Pack Quantity: 1
• For Use With: ADP1048

ADP1047/ADP1048
POWER METERING GAIN TRIM FOR HIGH LINE INPUT REGISTER
Table 154. Register 0xFE8F—Power Metering Gain Trim for High Line Input
Bits
7
[6:0]
CURRENT LOOP FILTER GAIN FOR LOW LINE INPUT AND LIGHT LOAD REGISTER
Table 155. Register 0xFE90—Current Loop Filter Gain for Low Line Input and Light Load
Bits
[7:0]
CURRENT LOOP FILTER ZERO FOR LOW LINE INPUT AND LIGHT LOAD REGISTER
Table 156. Register 0xFE91—Current Loop Filter Zero for Low Line Input and Light Load
Bits
[7:0]
CURRENT LOOP FILTER GAIN FOR HIGH LINE INPUT AND LIGHT LOAD REGISTER
Table 157. Register 0xFE92—Current Loop Filter Gain for High Line Input and Light Load
Bits
[7:0]
CURRENT LOOP FILTER ZERO FOR HIGH LINE INPUT AND LIGHT LOAD REGISTER
Table 158. Register 0xFE93—Current Loop Filter Zero for High Line Input and Light Load
Bits
[7:0]
SMART VOUT POWER READING REGISTER
Table 159. Register 0xFE94—Smart VOUT Power Reading
Bits
[15:0]
Bit Name
Gain trim polarity
Power meter gain
trim
Bit Name
Current loop filter
gain for low line and
light load
Bit Name
Current loop filter
zero for low line and
light load
Bit Name
Current loop filter
gain for high line and
light load
Bit Name
Current loop filter
zero for high line and
light load
Bit Name
Power reading
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
Description
These bits set the current loop digital filter gain of the PFC current loop under the low line
input voltage at a light load condition if Bit 5 of Register 0xFE4F is set to 1.
Description
These bits set the current loop digital filter zero of the PFC current loop under the low line
input voltage at a light load condition if Bit 5 of Register 0xFE4F is set to 1.
Description
These bits set the current loop digital filter gain of the PFC current loop under the high line
input voltage at a light load condition if Bit 5 of Register 0xFE4F is set to 1.
These bits set the current loop digital filter zero of the PFC current loop under the high line
input voltage at a light load condition if Bit 5 of Register 0xFE4F is set to 1.
Return the average power reading for smart output voltage (averaged over 16 full line cycles).
Description
1 = negative gain trim is introduced.
0 = positive gain trim is introduced.
This value calibrates the power meter gain at the high line input voltage. Each LSB corresponds
to 0.0625/128 of the input power.
Description
Description
Rev. 0 | Page 80 of 84
Data Sheet