ADP1048DC1-EVALZ Analog Devices, ADP1048DC1-EVALZ Datasheet - Page 31

• Manufacturer Part Number: ADP1048DC1-EVALZ
• Description: Daughter Cards & OEM Boards ADP1048 DAUGHTERCARD
• Manufacturer: Analog Devices
• Series: ADP1048r

Specifications of ADP1048DC1-EVALZ

• Rohs: yes
• Product: Daughter Cards
• Description/function: 100 kHz daughter board
• Dimensions: 40 mm x 25 mm
• Interface Type: I2C
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 3.3 V
• Factory Pack Quantity: 1
• For Use With: ADP1048

Data Sheet
Three load lines address super high line, high line, and low line
input voltage conditions.
When the rms value of the input voltage is higher than the super
high line input (for example, 250 V), the load line is flat, that is,
the output voltage remains at VOH, which is independent of the
power. To avoid output voltage oscillation when the input voltage
is around the super high line level, voltage hysteresis can be
programmed using Register 0xFE4D. It is recommended that
at least 16 V of hysteresis be programmed.
When the rms value of the input voltage is lower than the super
high line input but higher than the high line threshold, there is
a load line between P1 and P2 in terms of power. The output
voltage varies between VOH1 and VOH2 as a linear function
of the output power when the output power falls within the
range between P1 and P2. The power levels of P1 and P2 are
programmable using Register 0xFE44 and Register 0xFE45,
respectively. When the power is below P1, the output voltage
remains unchanged at VOH1. When the power is higher than
P2, the output voltage remains unchanged at VOH2.
The bottom load line in Figure 29 applies when the rms value of
the input voltage is lower than the low line threshold. The output
voltage varies between VOL1 and VOL2 as a linear function of
the output power when the output power falls within the range
between P1 and P2. When the power is below P1, the output
voltage remains unchanged at VOL1. When the power is higher
than P2, the output voltage remains unchanged at VOL2.
The user can program values for VOH, VOH2, VOH1, VOL2, and
VOL1 using Register 0xFE4A, Register 0xFE49, Register 0xFE48,
Register 0xFE47, and Register 0xFE46, respectively.
SMART SWITCHING FREQUENCY
For higher efficiency, the switching frequency of the ADP1047/
ADP1048
dition (see Figure 30). To enable the smart switching frequency
feature, set Register 0xFE4F, Bit 3, to 1.
The smart switching frequency feature uses two different
switching frequencies for heavy load and light load conditions.
When the output power is lower than the low power threshold,
P
put power is higher than P
switches at the normal set frequency, f
Hysteresis can be programmed in Register 0xFE4E. The user
can program the values for f
Register 0xFE32, respectively.
TH
, the PFC circuit switches at the f
f
SL
f
S
SWITCHING
FREQUENCY
can be programmed according to the load power con-
Figure 30. Smart Switching Frequency Control
P
TH
TH
SL
plus power hysteresis, the circuit
and P
TH
SL
frequency. When the out-
S
in Register 0xFE1C and
.
FULL POWER
POWER
Rev. 0 | Page 31 of 84
CURRENT LOOP FILTER FOR LIGHT LOAD
To achieve low THD under light load conditions, the ADP1047/
ADP1048
tion under both high line input and low line input (see Figure 31).
To enable the current loop filter for light load feature, set
Register 0xFE4F, Bit 5, to 1.
When the input power drops below the low power threshold, P
(set in Register 0xFE32), the current loop filter switches to the
light load filter after four full line cycles. When the input power
goes above P
filter switches back to the normal mode filter immediately. This
applies to both high line and low line input.
PHASE SHEDDING
To achieve high efficiency at light load, the
down one PWM output under light load conditions. When the
input power drops below the low power threshold, P
Register 0xFE32), one PWM output is disabled. When the input
power goes above the low power threshold plus power hysteresis
(set in Register 0xFE4E), the PWM resumes operation. To enable
phase shedding for the ADP1048, set Register 0xFE4F, Bit 4, to 1.
CURRENT LOOP FEEDFORWARD
Current loop feedforward is implemented in the ADP1047/
ADP1048
light load conditions (see Figure 32). To enable current loop
feedforward, set Register 0xFE4F, Bit 6, to 1.
HIGH/LOW LINE
THRESHOLD
AC LINE
Figure 31. Current Loop Filter at Light Load Condition
offer current loop filter presets for light load opera-
to improve the power factor and reduce THD under
I
LIGHT LOAD
LIGHT LOAD
LIGHT LOAD
REF
TH
HIGH LINE
LOW LINE
+
plus the programmed hysteresis, the current loop
I
L
Figure 32. Current Loop Feedforward
–
(ADP1048
THRESHOLD
POWER
H
I
(z)
–V
ADP1047/ADP1048
V
AC
REF
+
HIGH LINE
LOW LINE
ONLY)
+
DUTY CYCLE
ADP1048
INPUT POWER
TH
can shut
(set in
TH