ADP1048 Analog Devices, ADP1048 Datasheet
ADP1048
Related parts for ADP1048
ADP1048 Summary of contents
Page 1
... Data Sheet FEATURES Flexible digital power factor correction (PFC) controller Single phase operation (ADP1047); interleaved and bridgeless operation (ADP1048) True rms ac power metering Enhanced dynamic response Optimized light load efficiency performance Output voltage adjustment Frequency reduction Inrush current control Switching frequency spread spectrum for improved EMI ...
Page 2
... Pin Configurations and Function Descriptions ......................... 10 Functional Block Diagrams ........................................................... 11 Controller Architecture ................................................................. 12 Current Sense .............................................................................. 12 RMS Input Overcurrent Protection ......................................... 12 Fast Overcurrent Protection (ILIM Pin) ................................. 12 Current Balancing (IBAL Pin, ADP1048 Only) ..................... 14 Voltage Sense ............................................................................... 14 Overvoltage Protection .............................................................. 15 Power Factor Correction Control Loop ...................................... 17 Digital Compensation Filters .................................................... 17 Pulse-Width Modulation ........................................................... 18 Duty Cycle Minimum/Maximum Limits ...
Page 3
... Fast Voltage Loop Filter Gain Register ..................................... 68 Fast Voltage Loop Filter Zero Register ..................................... 68 Fast Voltage Loop Enable Register ............................................ 68 VAC_THRESHOLD_SET Register .......................................... 69 VAC_THRESHOLD_READ Register ...................................... 69 Rev Page ADP1047/ADP1048 ...
Page 4
... Load Register .............................................................................. 80 Current Loop Filter Zero for High Line Input and Light Load Register .............................................................................. 80 Smart VOUT Power Reading Register .................................... 80 IBAL Configuration Register (ADP1048 Only) ..................... 81 Debug Flag Registers .................................................................. 81 Outline Dimensions ....................................................................... 83 Ordering Guide .......................................................................... 83 Rev Page Data Sheet ...
Page 5
... SDA 5 20 ILIM SCL 6 19 IBAL SYNC CS– INRUSH 17 PGOOD 9 CS DGND AC_OK 15 11 PSON PWM2 14 12 VCORE PWM 13 ADP1048 Figure 2. Typical Interleaved Application, Rev Page ADP1047/ADP1048 operate from a single 3.3 V supply. The V OUT BULK CAPACITOR 3.3V PMBus ADP1048 ...
Page 6
... ADP1047/ADP1048 SPECIFICATIONS VDD = 3 −40°C to +85°C, unless otherwise noted. A Table 1. Parameter Symbol POWER SUPPLY Operating Supply Voltage VDD Supply Current I Supply Current for Programming I Shutdown Current I POWER-ON RESET Power-On Reset Undervoltage Lockout UVLO Overvoltage Lockout OVLO VCORE PIN Output Voltage Range ...
Page 7
... Data Sheet Parameter Symbol Voltage Sense Measurement Accuracy IBAL PIN (ADP1048 ONLY) Input Voltage Range Equivalent Resolution Channel Mismatch POWER METER Measurement Accuracy SWITCHING FREQUENCY Frequency Range Accuracy OSCILLATOR, CLOCK, AND PLL Oscillator Frequency Digital Clock Frequency PLL Frequency RES PIN ...
Page 8
... ADP1047/ADP1048 Parameter Symbol SDA, SCL PINS Input Low Voltage Input High Voltage Output Low Voltage Pull-Up Current Leakage Current SERIAL BUS TIMING Clock Frequency Glitch Immunity t Bus Free Time t Start Condition Hold Time t Start Condition Setup Time t Stop Condition Setup Time ...
Page 9
... V 2.7 V Table 3. Thermal Resistance −0 VDD + 0.3 V Package Type −0 VDD + 0.3 V 24-Lead QSOP (RQ-24) −0 +0.3 V −40°C to +85°C −65°C to +150°C ESD CAUTION 150°C 240°C 260°C Rev Page ADP1047/ADP1048 θ θ Unit JA JC 44.4 6.4 °C/W ...
Page 10
... Output of 2.5 V Regulator. Connect a 100 nF capacitor from VCORE to DGND. 13 PWM PWM Output for PFC Regulation. The PWM signal is referred to AGND. 14 PWM2 Auxiliary PWM Output (ADP1047) or Interleaved PWM Output (ADP1048). The PWM2 signal is referred to AGND. 15 AC_OK Open-Drain Output. User-configurable signal from a combination of flags. The AC_OK signal is referred to AGND. 16 PGOOD Open-Drain Output ...
Page 11
... PWM ENGINE DIGITAL CORE 8kB EEPROM INTERFACE ADC VREF ADD RTD AGND DGND Figure 6. ADP1048 Functional Block Diagram Rev Page ADP1047/ADP1048 OVP + – PGND DAC OVP PGOOD AC_OK SYNC OSC PSON SCL SDA OVP + – PGND DAC OLP OVP ...
Page 12
... Current Sense Gain and Offset Trim section). This calibration can be performed in the production environment; the settings are saved in the EEPROM of the ADP1047/ADP1048. The output of the Σ-Δ ADC is used for the following purposes: • The output is decimated at the switching frequency for the control loop. The effective number of bits (ENOB) is > ...
Page 13
... Figure 9. Level Shifting and Threshold for OCP Rev Page ADP1047/ADP1048 I M PGND OCP 1500mV ADP1047/ADP1048 LEVEL SHIFTING 10k × 80µA = 0.8V Comments Register 0xFE3D, Bits[4:3] Blanking from the leading edge; Register 0xFE3D, Bits[2:0] Fixed value; does not include blanking or debounce ...
Page 14
... Output Voltage (VFB) Calibration and Trim section). This calibration can be performed in the production environment; the settings are saved in the EEPROM of the ADP1047/ADP1048. Input Voltage Sensing (VAC Pin) The VAC pin is used for the monitoring and protection of the rectified power supply input voltage ...
Page 15
... Minimum duration of pulse to be considered; programmable using Register 0xFE31, Bits[1:0] Duration of time while the comparator is blanked and the threshold changes from rising to falling Does not include blanking or debounce Programmable using Register 0xFE2F, Bits[6:0] Programmable using Register 0xFE30, Bits[6:0] Register 0xFE01, Bits[7:6] Rev Page ADP1047/ADP1048 ...
Page 16
... ADP1047/ADP1048 Figure 12 shows an example of the output voltage and the OVP thresholds set. The rising and falling thresholds, FAST_OVP_ FAULT_RISE and FAST_OVP_FAULT_FALL, respectively, are used for fast OVP protection. FAST_OVP_FAULT_RISE corresponds to OVP , which is the trip point for overvoltage UP protection (see Figure 13). FAST_OVP_FAULT_FALL corre- sponds to OVP , which is the reset point for the fast OVP ...
Page 17
... Register 0xFE35; the low line threshold is programmed in Register 0xFE36.) The ADP1047/ADP1048 voltage at each half line cycle. When a transition between the high and low line threshold is detected, the part waits for four full line cycles before switching to the correct filter at the zero crossing of the input line cycle ...
Page 18
... PULSE-WIDTH MODULATION The ADP1047/ADP1048 trailing edge modulation. Trailing edge modulation is the more popular modulation scheme. Using trailing edge modulation, the rms ripple current in the bulk capacitors can be reduced when used with downstream converter synchronization ...
Page 19
... Rev Page ADP1047/ADP1048 Frequency Setting Frequency (Decimal) (kHz) 48 277.78 49 284.09 50 290.70 51 297.62 52 304.88 53 312.50 54 320.51 55 328.95 56 337.84 57 347.22 58 357.14 59 367.65 60 378 ...
Page 20
... Table 18). AC LINE DETECTION The ADP1047/ADP1048 are capable of detecting several parameters of the ac line input voltage and taking the appro- priate programmed actions when necessary. The detection is a combination of time and voltage measurements and is implemented via the VAC pin, which detects the rectified ac input voltage ...
Page 21
... VIN_ON = 85V (REG 0x35) AC VIN_UV_WARN_LIMIT = 80V (REG 0x58) AC VIN_OFF = 70V (REG 0x36) AC VIN_UV_FAULT_LIMIT = 70V (REG 0x59) AC Figure 20. Input Voltage Limits Rev Page ADP1047/ADP1048 VIN_OFF (REG 0x36) TIMER TIMER 1/4 1/4 Figure 19. AC Line Early Fault Detection VAC = 265V MAX AC HYSTERESIS ZONE VAC ...
Page 22
... LINE FAULT PROTECTIONS Line faults occur when the ac line is not behaving correctly and include anomalies such as a missing ac line cycle (can be partial), brownout, or high distortion levels. When a line fault occurs, the ADP1047/ADP1048 according to the situation. INRUSH DELAY TIME = 2 (REG 0xFE2E[2:0]) SOFT START ...
Page 23
... INRUSH DELAY TIME (REG 0xFE2E[2:0]) VOUT_UV_FAULT_LIMIT (REG 0x44) Figure 22. Line Fault (Missing Cycles) Timing Diagram SHUTDOWN Rev Page ADP1047/ADP1048 VIN_ON (REG 0x35) VIN_OFF (REG 0x36) SOFT START TIME (REG 0xFE2D[2:0]) ...
Page 24
... ADP1047/ADP1048 ADVANCED INPUT POWER METERING The ADP1047/ADP1048 monitor and communicate critical information, including input and output voltage, input and output current, temperature, and efficiency. They also monitor and communicate OVP, UVP, OCP, OTP, and open-loop protec- 2 tion functions interface reads all these values and flags and programs their thresholds ...
Page 25
... Reading a latched register resets the flags in that register. The latched fault registers are Register 0xFE80, Register 0xFE81, and Register 0xFE82. Rev Page ADP1047/ADP1048 Action Programmable Programmable Can set AC_OK flag ...
Page 26
... IF FLAG STILL ACTIVE 01 = SHUT DOWN (AFTER DEBOUNCE IMMEDIATE SHUTDOWN Figure 25. Standard PMBus Fault Response ADP1047/ADP1048 Description Power supply on signal: this flag indicates that the PSON signal (hardware or software) is inactive. General output overvoltage fault. This flag is a combination (OR) of any output overvoltage flag: Register 0x7A[7] and Register 0xFE80[4] (FAST_OVP) ...
Page 27
... For example, if one fault has a retry setting programmed to 011 and the other has a retry setting of 001, the lower number of retries is executed. Rev Page ADP1047/ADP1048 Action Programmable Programmable Programmable ...
Page 28
... ADP1047/ADP1048 MANUFACTURER-SPECIFIC FLAG RESPONSE Manufacturer-specific flags follow a different response from the standard PMBus flags because these flags are much faster and, in some cases, operate on a pulse-by-pulse basis. FAST OCP Flag Response (Register 0xFE00) The fast OCP flag responds to an overcurrent condition that occurs on the comparator connected to the ILIM pin ...
Page 29
... Data Sheet MONITORING FUNCTIONS Voltage, current, power, and temperature measurements are taken by the ADP1047/ADP1048. These values are stored in the following registers and can be read through the PMBus interface. • Input voltage measurement (Register 0x88) • Output voltage measurement (Register 0x8B) • ...
Page 30
... Figure 29). To enable the smart output voltage feature, set Register 0xFE4F, Bit TIME VOH VOH2 VOH1 VOL2 VOL1 TIME 2/f DITHER Rev Page Data Sheet ADP1047/ADP1048 OUTPUT VOLTAGE SUPER HIGH LINE HIGH LINE LOW LINE P1 P2 100% Figure 29. Smart Output Voltage Control (Load Line) controllers. POWER ...
Page 31
... Register 0xFE32), one PWM output is disabled. When the input power goes above the low power threshold plus power hysteresis (set in Register 0xFE4E), the PWM resumes operation. To enable phase shedding for the ADP1048, set Register 0xFE4F, Bit CURRENT LOOP FEEDFORWARD Current loop feedforward is implemented in the ADP1047/ ADP1048 light load conditions (see Figure 32) ...
Page 32
... IBAL SYNC CS– INRUSH 17 PGOOD 9 CS+ 16 DGND AC_OK 10 15 PSON PWM2 VCORE PWM 13 ADP1048 Figure 33. Schematic of Bridgeless PFC Circuit with the VAC PWM Figure 34. Bridgeless Boost Operation Rev Page OUT T2 BULK CAPACITOR Q2 3.3V PMBus ADP1048 Data Sheet ...
Page 33
... READ_PIN register (Register 0x97) equals the measured result of the input power from the calibrated equipment. For input power offset trim, adjust the values in Register 0xFE33 (for low line input) and Register 0xFE8E (for high line input). Rev Page ADP1047/ADP1048 ...
Page 34
... PMBus command set. The list of standard PMBus and manufacturer-specific commands can be found in the Standard PMBus Commands Supported by the ADP1047/ADP1048 section and the Manufacturer-Specific PMBus Command section. PMBus ADDRESS Control of the interface ...
Page 35
... ADDRESS Figure 40. Read Word Protocol COMMAND BYTE COUNT DATA BYTE 1 CODE = N Figure 41. Block Write Protocol Rev Page ADP1047/ADP1048 ADP1047 ADP1048 / follow one of the protocol Figure 36 through Figure 42 . The command code extension, 0xFE The extended command code, 0x00 to 0xFF ...
Page 36
... MASTER TO SLAVE SLAVE TO MASTER Clock Generation and Stretching The ADP1047/ADP1048 are always PMBus slave devices in the overall system; therefore, the device never needs to generate the clock, which is done by the master device in the system. How- ever, the PMBus slave device is capable of clock stretching to put the master in a wait state ...
Page 37
... PMBus slave considers this a data content fault and responds as follows: • Sends all 1s (0xFF) as long as the host continues to request data • Sets the CML bit in the STATUS_BYTE register Note that this is the same error described in the Host Reads Too Many Bytes (Item 10.8.6) section. Rev Page ADP1047/ADP1048 ...
Page 38
... OVERVIEW The EEPROM controller provides an interface between the ADP1047/ADP1048 core logic and the built-in Flash/EE. The user can control data access to and from the EEPROM through this controller interface. Separate PMBus commands are avail- able for the read, write, and erase operations to the EEPROM ...
Page 39
... The factory default settings are stored in Page 0 of the EEPROM main block. The factory settings can be downloaded from the EEPROM into the internal registers using the RESTORE_ DEFAULT_ALL command (Command Code 0x12). When this command is executed, the EEPROM password is also reset to the factory default setting of 0xFF. Rev Page ADP1047/ADP1048 ...
Page 40
... ADP1047/ADP1048 SAVING REGISTER SETTINGS INTO EEPROM The register settings cannot be saved to the factory scratch pad located in Page 0 of the EEPROM main block. This is to prevent the user from accidentally overriding the factory trim settings and default register settings. Save Register Settings to the User Scratch Pad ...
Page 41
... Data Sheet SOFTWARE GUI A free software GUI is available for programming and config- uring the ADP1047/ADP1048. The GUI is designed to be intuitive and dramatically reduces power supply design and development time. The software includes filter design and power supply PWM topology windows. The GUI is also an information center, displaying the status of all readings, monitoring, and flags on the ADP1047/ADP1048 ...
Page 42
... ADP1047/ADP1048 STANDARD PMBus COMMANDS SUPPORTED BY THE Table 15 lists the standard PMBus commands that are implemented on the ADP1047/ADP1048. Many of these commands are implemented in registers, which share the same hexadecimal value as the PMBus command code. Table 15. Standard PMBus Commands Command Code Command Name ...
Page 43
... Data Sheet MANUFACTURER-SPECIFIC PMBus COMMANDS Table 16 lists the manufacturer-specific PMBus commands that are implemented on the ADP1047/ADP1048. These commands are implemented in registers, which share the same hexadecimal value as the PMBus command code. Table 16. Manufacturer-Specific Commands Command Code Command Name 0xFE00 CS_FAST_OCP_RESPONSE 0xFE01 ...
Page 44
... Current loop filter zero for high line input and light load Command Code Command Name 0xFE94 Smart VOUT power reading 0xFE95 IBAL configuration 0xFE96 Debug Flag 0 0xFE97 Debug Flag 1 0xFE98 Debug Flag 2 0xFE99 Debug Flag 3 0xFE9A Debug Flag 4 0xFE9B Debug Flag 5 Rev Page Data Sheet (ADP1048 only) ...
Page 45
... Setting this bit disables writes to all commands except for WRITE_PROTECT. Setting this bit disables writes to all commands except for WRITE_PROTECT, OPERATION, and EEPROM_PAGE_ERASE. Setting this bit disables writes to all commands except for WRITE_PROTECT, OPERATION, EEPROM_PAGE_ERASE, ON_OFF_CONFIG, and VOUT_COMMAND. Reserved. Rev Page ADP1047/ADP1048 ...
Page 46
... ADP1047/ADP1048 RESTORE_USER_ALL COMMAND Code 0x16, send byte, no data. This command downloads the stored user settings from EEPROM into operating memory. CAPABILITY REGISTER This register allows host systems to determine the capabilities of the PMBus device. Table 20. Register 0x19—CAPABILITY Bits Bit Name R/W 7 Packet error ...
Page 47
... Shut down, disable the output, and retry the number of times specified by the retry setting (Bits[5:3]). 1 1 Disable the output and wait for the fault to clear. After the fault is cleared, reenable the output. Rev Page ADP1047/ADP1048 The exponent (N) is set in the N ) ...
Page 48
... ADP1047/ADP1048 Bits Bit Name R/W [5:3] Retry setting R/W [2:0] Delay times R/W VOUT_OV_WARN_LIMIT REGISTER This register sets the accurate overvoltage threshold measured at the PFC output that causes an overvoltage warning condition. Table 29. Register 0x42—VOUT_OV_WARN_LIMIT Bits Bit Name R/W [15:11] Exponent R [10:8] High bits R/W [7:0] Low byte R/W VOUT_UV_WARN_LIMIT REGISTER This register sets the undervoltage threshold measured at the PFC output that causes an undervoltage warning condition. ...
Page 49
... Shut down, disable the output, and retry the number of times specified by the retry setting (Bits[5:3]). 1 1 Disable the output and wait for the fault to clear. After the fault is cleared, reenable the output. Rev Page ADP1047/ADP1048 Delay Time 2 252 ms 558 ms 924 ms 1260 ms 1596 ms ...
Page 50
... ADP1047/ADP1048 Bits Bit Name R/W [5:3] Retry setting R/W [2:0] Delay times R/W VIN_OV_FAULT_LIMIT REGISTER This register sets the overvoltage threshold measured at the PFC input that causes an overvoltage fault condition. Table 34. Register 0x55—VIN_OV_FAULT_LIMIT Bits Bit Name R/W [15:11] Exponent R [10:8] High bits R/W [7:0] Low byte R/W VIN_OV_FAULT_RESPONSE REGISTER This register instructs the device on actions to take due to an input overvoltage fault condition. ...
Page 51
... Return the exponent (N) used in VIN linear mode format ( × 2 exponent register (Register 0xFE39, Bits[5:3]). Mantissa high bits (Y[10:8]) used in VIN linear mode format ( × 2 Mantissa low byte (Y[7:0]) used in VIN linear mode format ( × 2 exponent register (Register 0xFE39, Bits[5:3]). Rev Page ADP1047/ADP1048 Delay Time 2 252 ms 558 ms 924 ms 1260 ms ...
Page 52
... ADP1047/ADP1048 VIN_UV_FAULT_RESPONSE REGISTER This register instructs the device on actions to take due to an input undervoltage fault condition. Table 38. Register 0x5A—VIN_UV_FAULT_RESPONSE Bits Bit Name R/W [7:6] Response R/W [5:3] Retry setting R/W [2:0] Delay times R/W IIN_OC_FAULT_LIMIT REGISTER This register sets the accurate overcurrent threshold measured at the PFC input that causes an overcurrent fault condition. ...
Page 53
... Return the exponent (N) used in current linear mode format ( × 2 exponent register (Register 0xFE39, Bits[10:6]). Mantissa high bits (Y[10:8]) used in current linear mode format ( × 2 Mantissa low byte (Y[7:0]) used in current linear mode format ( × 2 Rev Page ADP1047/ADP1048 Delay Time 2 252 ms 558 ms 924 ms ...
Page 54
... ADP1047/ADP1048 PIN_OP_WARN_LIMIT REGISTER This register sets the upper input power (W) threshold that causes an input overpower warning condition. Table 42. Register 0x6B—PIN_OP_WARN_LIMIT Bits Bit Name R/W [15:11] Exponent R [10:8] High bits R/W [7:0] Low byte R/W STATUS_BYTE REGISTER This register returns the lower byte of the STATUS_WORD register. A value this register indicates that a fault has occurred. ...
Page 55
... Mantissa high bits (Y[10:8]) used in current linear mode format ( × 2 [7:0] Low byte R Mantissa low byte (Y[7:0]) used in current linear mode format ( × Rev Page ADP1047/ADP1048 N ). The exponent is set in the The exponent (N) is set in the N ). The exponent is set in the N ) ...
Page 56
... ADP1047/ADP1048 READ_VOUT REGISTER This register returns the output voltage (V) in VIN linear mode format ( × 2 Table 50. Register 0x8B—READ_VOUT Bits Bit Name R/W Description [15:11] Exponent R Return the exponent (N) used in VOUT linear mode format ( × 2 VOUT_MODE register (Register 0x20, Bits[2:0]). The exponent is in twos complement format. ...
Page 57
... Write the password to this register to unlock the trim registers for write access. Write the trim password twice (default 0x00) to unlock the register; write any other value to exit. EEPROM_INFO COMMAND Code 0xF1, block read/write. This command reads the manufacturer’s data from the EEPROM. Rev Page ADP1047/ADP1048 ...
Page 58
... ADP1047/ADP1048 CS_FAST_OCP_RESPONSE REGISTER This register instructs the device on actions to take due to a fast overcurrent protection condition. Table 62. Register 0xFE00—CS_FAST_OCP_RESPONSE Bits Bit Name R/W [7:6] Response R/W [5:4] N-time R/W [3:0] RSVD R OVP_FAST_OVP_RESPONSE REGISTER This register instructs the device on actions to take due to a fast overvoltage fault condition. ...
Page 59
... Debounce time, R/W Debounce from high to low for the AC_OK pin. AC_OK pin Bit 5 (high to low Bit 6 Time 200 ms 0 320 ms 1 600 ms Bit 4 Time 200 ms 0 320 ms 1 600 ms Rev Page ADP1047/ADP1048 ...
Page 60
... ADP1047/ADP1048 Bits Bit Name R/W Description [3:2] Debounce time, R/W Debounce from low to high for the PGOOD pin. PGOOD pin Bit 3 (low to high [1:0] Debounce time, R/W Debounce from high to low for the PGOOD pin. PGOOD pin Bit 1 (high to low PSON_SET REGISTER This register sets the delay time for PSON and PSOFF. Table 68. Register 0xFE06— ...
Page 61
... Table 73. Register 0xFE0B—AC_OK_FLAGS_LIST Bits Bit Name R/W Description 7 VIN_UV_FAULT R ignore VIN_UV_FAULT flag. 6 VIN_UV_WARN R ignore VIN_UV_WARN flag. 5 IIN_OC_FAULT R ignore IIN_OC_FAULT flag. 4 IIN_OC_WARN R ignore IIN_OC_WARN flag. 3 FAST_OCP R ignore FAST_OCP flag. 2 AC_LINE_PERIOD R ignore AC_LINE_PERIOD flag. 1 BROWN_OUT R ignore BROWN_OUT flag. 0 INRUSH R ignore INRUSH flag. Rev Page ADP1047/ADP1048 ...
Page 62
... ADP1047/ADP1048 PWM AND PWM2 TIMING REGISTERS Register 0xFE0C through Register 0xFE13 configure the rising and falling edges of the PWM outputs. Table 74. Register 0xFE0C—PWM Rising Edge Timing (PWM Pin) Bits Bit Name R/W Description [7:0] t R/W This register contains the eight MSBs of the 10-bit t 1 Table 75. Register 0xFE0D— ...
Page 63
... The LSBs are specified in Register 0xFE17. Description These eight bits are the LSBs of the 9-bit value that sets the amount of offset trim applied to the RTD ADC reading. The MSB is specified in Register 0xFE16, Bit 0. Rev Page ADP1047/ADP1048 time. This value is always used with the eight 2 time. 2 right ...
Page 64
... ADP1047/ADP1048 RTD ADC GAIN TRIM SETTING REGISTER This register must be unlocked for write access; see Table 61. Table 86. Register 0xFE18—RTD ADC Gain Trim Setting Bits Bit Name R/W 7 Gain polarity R/W [6:0] RTD ADC gain trim R/W OT_FAULT_LIMIT REGISTER This register sets the overtemperature fault threshold. The debounce time of the overtemperature fault flag is 100 ms. ...
Page 65
... Rev Page ADP1047/ADP1048 Bit 1 Bit 0 Frequency (kHz 30. 32. 35. 39. 43. 48. 52. 55. 60. 65. 71. 78. 86.81 ...
Page 66
... ADP1047/ADP1048 Bits Bit Name R/W [5:0] Switching frequency R/W LOW POWER SWITCHING FREQUENCY SETTING REGISTER This register sets the PFC switching frequency when the PFC is running under low power mode and the smart switching frequency operation is enabled. Table 90. Register 0xFE1C—Low Power Switching Frequency Setting ...
Page 67
... Description Reserved. Sets the period for updating the switching frequency. Each LSB corresponds to 40 μs. Rev Page ADP1047/ADP1048 Bit 1 Bit 0 Frequency (kHz 148. 156. 164. 173. 183. 195 ...
Page 68
... ADP1047/ADP1048 FREQUENCY SYNCHRONIZATION SET REGISTER Table 92. Register 0xFE1E—Frequency Synchronization Set Bits Bit Name R/W [7:2] RSVD R/W [1:0] Frequency division R/W VOLTAGE LOOP FILTER GAIN REGISTER Table 93. Register 0xFE20—Voltage Loop Filter Gain Bits Bit Name R/W [7:0] Voltage loop filter R/W gain VOLTAGE LOOP FILTER ZERO REGISTER Table 94. Register 0xFE21— ...
Page 69
... Register 0xFE25, Bit 7. Description These bits set the minimum ac line period of the input voltage. Each LSB corresponds to 163.84 μs resolution. Description These bits set the maximum ac line period of the input voltage. Each LSB corresponds to 163.84 μs resolution. Rev Page ADP1047/ADP1048 ...
Page 70
... ADP1047/ADP1048 CURRENT LOOP FILTER GAIN FOR LOW LINE INPUT REGISTER Table 102. Register 0xFE29—Current Loop Filter Gain for Low Line Input Bits Bit Name R/W [7:0] Current loop filter R/W gain for low line CURRENT LOOP FILTER ZERO FOR LOW LINE INPUT REGISTER Table 103. Register 0xFE2A— ...
Page 71
... This threshold is programmable from 1.5 V. Each LSB increments the threshold by 3.844 mV. A value of 0x00 corresponds threshold; a value of 0x3F corresponds to a 1.492 V threshold. Description Reserved. These bits set the fast OVP debounce time. Bit 1 Bit 0 Time 0 0 120 240 480 640 ns Rev Page ADP1047/ADP1048 ...
Page 72
... ADP1047/ADP1048 LOW POWER MODE OPERATION THRESHOLD REGISTER Table 111. Register 0xFE32—Low Power Mode Operation Threshold Bits Bit Name R/W [7:0] Low power threshold R/W POWER METERING OFFSET TRIM FOR LOW LINE INPUT REGISTER Table 112. Register 0xFE33—Power Metering Offset Trim for Low Line Input ...
Page 73
... Write the exponent (N) in twos complement format (K Reserved. Mantissa (Y[9:0]) used in K linear mode format (K VIN Description Write the exponent (N) in twos complement format (IIN_GSENSE = Y × 2 Reserved. Mantissa (Y[9:0]) used in IIN linear mode format (IIN_GSENSE = Y × 2 Rev Page ADP1047/ADP1048 × VIN × VIN N ) ...
Page 74
... ADP1047/ADP1048 CS FAST OCP BLANK REGISTER Table 122. Register 0xFE3D—CS Fast OCP Blank Bits Bit Name R/W [7:5] RSVD R [4:3] CS OCP debounce R/W time [2:0] Leading edge R/W blanking time CS FAST OCP SETTING REGISTER Table 123. Register 0xFE3E—CS Fast OCP Setting Bits Bit Name R/W [7:5] ILIM absolute value ...
Page 75
... These bits set the threshold value for high power mode operation when the smart output voltage function is enabled. When the input power is higher than this value, the output voltage is VOL2 for low line input and VOH2 for high line input. Rev Page ADP1047/ADP1048 ...
Page 76
... ADP1047/ADP1048 SMART VOUT LOW LINE (VOL1) REGISTER Table 131. Register 0xFE46—Smart VOUT Low Line (VOL1) Bits Bit Name R/W [15:11] RSVD R [10:0] VOL1 R/W SMART VOUT LOW LINE (VOL2) REGISTER Table 132. Register 0xFE47—Smart VOUT Low Line (VOL2) Bits Bit Name R/W [15:11] RSVD R [10:0] ...
Page 77
... This register determines the mantissa hysteresis for the VIN_UV_FAULT_LIMIT condition. This hysteresis applies only when the disable output option is selected as the VIN_UV_FAULT_ RESPONSE (Register 0x5A, Bits[7:6]). The PFC output is reenabled when the input voltage is higher than VIN_UV_FAULT_LIMIT plus this hysteresis. Rev Page ADP1047/ADP1048 ...
Page 78
... ADP1047/ADP1048 VAC ADC OFFSET TRIM REGISTER This register must be unlocked for write access; see Table 61. Table 143. Register 0xFE53—VAC ADC Offset Trim Bits Bit Name R/W [7:0] VAC ADC offset trim R/W CS ADC OFFSET TRIM FOR 500 mV RANGE REGISTER This register must be unlocked for write access; see Table 61. ...
Page 79
... Description Return the measured temperature in ADC 12-bit format. Description 1 = negative offset trim is introduced positive offset trim is introduced. This value calibrates the power meter offset at the high line input voltage. Each LSB corresponds to 0.0625/128 of the full input power. Rev Page ADP1047/ADP1048 ...
Page 80
... ADP1047/ADP1048 POWER METERING GAIN TRIM FOR HIGH LINE INPUT REGISTER Table 154. Register 0xFE8F—Power Metering Gain Trim for High Line Input Bits Bit Name R/W 7 Gain trim polarity R/W [6:0] Power meter gain R/W trim CURRENT LOOP FILTER GAIN FOR LOW LINE INPUT AND LIGHT LOAD REGISTER Table 155. Register 0xFE90— ...
Page 81
... VAC is smaller than the value in VIN_UV_WARN_LIMIT (Register 0x58 input voltage is higher than the high line threshold VAC is lower than the value stored in VIN_ON (Register 0x35 communications, memory, or logic fault overvoltage condition is present on the VDD rail. Rev Page ADP1047/ADP1048 ...
Page 82
... ADP1047/ADP1048 Table 164. Register 0xFE99—Debug Flag 3 Bits Bit Name R/W 7 VIN_OV_FAULT R 6 VCORE_OV R 5 PIN_OP_WARN R 4 AC_PERIOD R 3 IIN_OC_WARN R 2 IIN_OC_FAULT R 1 FAST_OCP R 0 INPUT R Table 165. Register 0xFE9A—Debug Flag 4 Bits Bit Name R/W 7 OLP R 6 FAST_OVP R 5 VOUT_UV_FAULT R 4 VOUT_UV_WARN ...
Page 83
... Dimensions shown in inches and (millimeters) Package Description 24-Lead Shrink Small Outline Package [QSOP] 24-Lead Shrink Small Outline Package [QSOP] ADP1047 300 W Evaluation Board ADP1048 600 W Evaluation Board ADP1047 Daughter Card ADP1048 Daughter Card USB Adapter Rev Page ADP1047/ADP1048 0 ...
Page 84
... ADP1047/ADP1048 NOTES refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors). ©2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09696-0-9/11(0) Rev Page Data Sheet ...