ADP1048DC1-EVALZ Analog Devices, ADP1048DC1-EVALZ Datasheet - Page 75

• Manufacturer Part Number: ADP1048DC1-EVALZ
• Description: Daughter Cards & OEM Boards ADP1048 DAUGHTERCARD
• Manufacturer: Analog Devices
• Series: ADP1048r

Specifications of ADP1048DC1-EVALZ

• Rohs: yes
• Product: Daughter Cards
• Description/function: 100 kHz daughter board
• Dimensions: 40 mm x 25 mm
• Interface Type: I2C
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 3.3 V
• Factory Pack Quantity: 1
• For Use With: ADP1048

Data Sheet
VAC ADC GAIN TRIM REGISTER
This register must be unlocked for write access; see Table 61.
Table 125. Register 0xFE40—VAC ADC Gain Trim
Bits
7
[6:0]
VFB ADC GAIN TRIM REGISTER
This register must be unlocked for write access; see Table 61.
Table 126. Register 0xFE41—VFB ADC Gain Trim
Bits
7
[6:0]
CS ADC GAIN TRIM FOR 500 mV RANGE REGISTER
This register must be unlocked for write access; see Table 61.
Table 127. Register 0xFE42—CS ADC Gain Trim for 500 mV Range
Bits
7
[6:0]
IBAL GAIN REGISTER
Table 128. Register 0xFE43—IBAL Gain
Bits
7
[6:0]
SMART VOUT LOW POWER THRESHOLD (P1) REGISTER
Table 129. Register 0xFE44—Smart VOUT Low Power Threshold (P1)
Bits
[15:13]
[12:0]
SMART VOUT HIGH POWER THRESHOLD (P2) REGISTER
Table 130. Register 0xFE45—Smart VOUT High Power Threshold (P2)
Bits
[15:13]
[12:0]
Bit Name
Gain polarity
VAC ADC gain trim
Bit Name
Gain polarity
VFB ADC gain trim
Bit Name
Gain polarity
CS ADC gain trim
Bit Name
IBAL enable
IBAL gain
Bit Name
RSVD
P1
Bit Name
RSVD
P2
(ADP1048
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R/W
R/W
R
R/W
ONLY)
(ADP1048
Description
1 = negative gain is introduced.
0 = positive gain is introduced.
This value calibrates the VAC voltage sense gain.
Description
1 = negative gain is introduced.
0 = positive gain is introduced.
This value calibrates the output voltage sense gain.
Description
1 = negative gain is introduced.
0 = positive gain is introduced.
This value calibrates the CS current sense gain.
Description
1 = enable current balancing.
0 = disable current balancing and reset the IBAL integrator.
The gain can be set from 0 to 127.
Description
Reserved.
These bits set the threshold value for low power mode operation when the smart output
voltage function is enabled. When the input power is lower than this value, the output voltage
is VOL1 for low line input and VOH1 for high line input.
Description
Reserved.
These bits set the threshold value for high power mode operation when the smart output
voltage function is enabled. When the input power is higher than this value, the output
voltage is VOL2 for low line input and VOH2 for high line input.
Only)
Rev. 0 | Page 75 of 84
ADP1047/ADP1048