AT25DF321A-SH-B Atmel, AT25DF321A-SH-B Datasheet - Page 9

• Manufacturer Part Number: AT25DF321A-SH-B
• Description: IC FLASH 32MBIT 100MHZ 8SOIC
• Manufacturer: Atmel

Specifications of AT25DF321A-SH-B

• Format - Memory: FLASH
• Memory Type: DataFLASH
• Memory Size: 32M (16384 pages x 256 Bytes)
• Speed: 100MHz
• Interface: SPI, RapidS
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (5.3mm Width), 8-SOP, 8-SOEIAJ
• Memory Configuration: 16384 Pages X 256 Bytes
• Interface Type: Serial, SPI
• Clock Frequency: 100MHz
• Supply Voltage Range: 2.7V To 3.6V
• Memory Case Style: SOIC
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

3686D–DFLASH–12/09
Figure 7-2.
Figure 7-3.
7.2
SCK
SCK
SO
SO
CS
CS
SI
SI
Dual-Output Read Array
The Dual-Output Read Array command is similar to the standard Read Array command and can be used to sequentially
read a continuous stream of data from the device by simply providing the clock signal once the initial starting address has
been specified. Unlike the standard Read Array command, however, the Dual-Output Read Array command allows two
bits of data to be clocked out of the device on every clock cycle rather than just one.
The Dual-Output Read Array command can be used at any clock frequency up to the maximum specified by f
perform the Dual-Output Read Array operation, the CS pin must first be asserted and the opcode of 3Bh must be clocked
into the device. After the opcode has been clocked in, the three address bytes must be clocked in to specify the starting
address location of the first byte to read within the memory array. Following the three address bytes, a single dummy byte
must also be clocked into the device.
After the three address bytes and the dummy byte have been clocked in, additional clock cycles will result in data being
output on both the SO and SIO pins. The data is always output with the MSB of a byte first, and the MSB is always output
on the SO pin. During the first clock cycle, bit 7 of the first data byte will be output on the SO pin while bit 6 of the same
data byte will be output on the SIO pin. During the next clock cycle, bits 5 and 4 of the first data byte will be output on the
SO and SIO pins, respectively. The sequence continues with each byte of data being output after every four clock cycles.
When the last byte (3FFFFFh) of the memory array has been read, the device will continue reading back at the beginning
of the array (000000h). No delays will be incurred when wrapping around from the end of the array to the beginning of
the array.
Deasserting the CS pin will terminate the read operation and put the SO and SIO pins into a high-impedance state. The CS
pin can be deasserted at any time and does not require that a full byte of data be read.
Read Array – 0Bh Opcode
Read Array – 03h Opcode
HIGH-IMPEDANCE
HIGH-IMPEDANCE
MSB
MSB
0
0
0
0
0
0
1
1
0
0
2
2
OPCODE
OPCODE
0
0
3
3
1
0
4
4
0
0
5
5
1
1
6
6
1
1
7
7
MSB
MSB
A
A
8
8
A
A
9
9
ADDRESS BITS A23-A0
ADDRESS BITS A23-A0
A
A
10 11
10 11
A
A
A
A
12
12
A
A
A
A
29 30
29 30
A
A
A
A
31 32
31 32
MSB
MSB
X
D
D
X
33
33
DATA BYTE 1
DON'T CARE
D
X
34
34
X
D
35
35
X
D
36
36
X
D
37 38
37 38
X
D
X
D
39
39 40
MSB
MSB
D
D
40
D
D
41
DATA BYTE 1
D
42 43
D
Atmel AT25DF321A
D
44
D
45
D
46
D
47 48
MSB
D
D
RDDO
. To
9