AT25DF321A-SH-B Atmel, AT25DF321A-SH-B Datasheet - Page 41

• Manufacturer Part Number: AT25DF321A-SH-B
• Description: IC FLASH 32MBIT 100MHZ 8SOIC
• Manufacturer: Atmel

Specifications of AT25DF321A-SH-B

• Format - Memory: FLASH
• Memory Type: DataFLASH
• Memory Size: 32M (16384 pages x 256 Bytes)
• Speed: 100MHz
• Interface: SPI, RapidS
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (5.3mm Width), 8-SOP, 8-SOEIAJ
• Memory Configuration: 16384 Pages X 256 Bytes
• Interface Type: Serial, SPI
• Clock Frequency: 100MHz
• Supply Voltage Range: 2.7V To 3.6V
• Memory Case Style: SOIC
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

3686D–DFLASH–12/09
13.
Atmel RapidS Implementation
To implement Atmel
implementation, a full clock cycle can be used to transmit data back and forth across the serial bus. The Atmel
AT25DF321A is designed to always clock its data out on the falling edge of the SCK signal and clock data in on the rising
edge of SCK.
For full clock cycle operation to be achieved, when the AT25DF321A is clocking data out on the falling edge of SCK, the
host controller should wait until the next falling edge of SCK to latch the data in. Similarly, the host controller should clock its
data out on the rising edge of SCK in order to give the AT25DF321A a full clock cycle to latch the incoming data in on the
next rising edge of SCK.
Implementing RapidS allows a system to run at higher clock frequencies since a full clock cycle is used to accommodate a
device’s clock-to-output time, input setup time, and associated rise/fall times. For example, if the system clock frequency is
100MHz (10ns cycle time) with a 50% duty cycle, and the host controller has an input setup time of 2ns, then a standard
SPI implementation would require that the slave device be capable of outputting its data in less than 3ns to meet the 2ns
host controller setup time [(10ns x 50%) – 2ns] not accounting for rise/fall times. In an SPI mode 0 or 3 implementation,
the SPI master is designed to clock in data on the next immediate rising edge of SCK after the SPI slave has clocked its data
out on the preceding falling edge. This essentially makes SPI a half-clock cycle protocol and requires extremely fast clock-
to-output times and input setup times in order to run at high clock frequencies. With a RapidS implementation of this
example, however, the full 10ns cycle time is available which gives the slave device up to 8ns, not accounting for rise/fall
times, to clock its data out. Likewise, with RapidS, the host controller has more time available to output its data to the slave
since the slave device would be clocking that data in a full clock cycle later.
Figure 13-1. Atmel RapidS Operation
Slave
MOSI = Master Out, Slave In
The Master is the ASIC/MCU and the Slave is the memory device.
The Master always clocks data out on the rising edge of SCK and always clocks data in on the falling edge of SCK.
The Slave always clocks data out on the falling edge of SCK and always clocks data in on the rising edge of SCK.
A.
B.
C. Master clocks out second bit of BYTE A on the same rising edge of SCK.
D. Last bit of BYTE A is clocked out from the Master.
E.
F.
G. Master clocks in first bit of BYTE B.
H. Slave clocks out second bit of BYTE B.
I.
MOSI
MISO
SCK
Master clocks out first bit of BYTE A on the rising edge of SCK.
Slave clocks in first bit of BYTE A on the next rising edge of SCK.
Last bit of BYTE A is clocked into the slave.
Slave clocks out first bit of BYTE B.
Master clocks in last bit of BYTE B.
CS
®
A
RapidS
1
B
MSB
™
MISO = Master In, Slave Out
C
2
and operate at clock frequencies higher than what can be achieved in a viable SPI
3
4
BYTE A
t
V
5
6
7
D
8
E
LSB
F
1
G
MSB
2
H
3
4
BYTE B
5
Atmel AT25DF321A
6
7
8
I
LSB
1
41