EVAL-AD5142ADBZ Analog Devices, EVAL-AD5142ADBZ Datasheet - Page 9

• Manufacturer Part Number: EVAL-AD5142ADBZ
• Description: Digital Potentiometer Development Tools EVALUATION BOARD I.C.
• Manufacturer: Analog Devices
• Series: AD5142Ar

Specifications of EVAL-AD5142ADBZ

• Rohs: yes
• Product: Evaluation Boards
• Tool Is For Evaluation Of: AD5142A
• Resistance: 10 kOhms/100 kOhms
• Operating Supply Voltage: 5.5 V
• Interface Type: I2C
• Maximum Operating Temperature: + 125 C
• Factory Pack Quantity: 1

Data Sheet
INTERFACE TIMING SPECIFICATIONS
V
Table 4.
Parameter
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
1
2
3
4
5
SCL
1
2
3
4
5
6
7
8
9
10
11
11A
12
SP
RESET
EEPROM_PROGRAM
EEPROM_READBACK
POWER_UP
RESET
Maximum bus capacitance is limited to 400 pF.
The SDA and SCL timing is measured with the input filters enabled. Switching off the input filters improves the transfer rate; however, it has a negative effect on the
EMC behavior of the part.
Input filtering on the SCL and SDA inputs suppresses noise spikes that are less than 50 ns for fast mode.
The EEPROM program time depends on the temperature and EEPROM write cycles. Higher timing is expected at lower temperatures and higher write cycles.
Maximum time after V
LOGIC
3
2
= 1.8 V to 5.5 V; all specifications T
5
1
4
Test Conditions/Comments
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Fast mode
0.1
DD
− V
SS
is equal to 2.3 V.
MIN
to T
Min
4.0
0.6
4.7
1.3
250
100
0
0
4.7
0.6
4
0.6
4.7
1.3
4
0.6
20 + 0.1 C
20 + 0.1 C
20 + 0.1 C
20 + 0.1 C
20 + 0.1 C
0
MAX
, unless otherwise noted.
L
L
L
L
L
Rev. A | Page 9 of 32
Typ
15
7
30
Max
100
400
3.45
0.9
1000
300
300
300
1000
300
1000
300
300
300
50
10
50
30
75
Unit
kHz
kHz
µs
µs
µs
µs
ns
ns
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ms
µs
µs
µs
Description
Serial clock frequency
SCL high time, t
SCL low time, t
Data setup time, t
Data hold time, t
Setup time for a repeated start condition, t
Hold time (repeated) for a start condition, t
Bus free time between a stop and a start condition, t
Setup time for a stop condition, t
Rise time of SDA signal, t
Fall time of SDA signal, t
Rise time of SCL signal, t
Rise time of SCL signal after a repeated start condition
and after an acknowledge bit, t
Fall time of SCL signal, t
Pulse width of suppressed spike (not shown in Figure 3)
RESET low time (not shown in Figure 3)
Memory program time (not shown in Figure 3)
Memory readback time (not shown in Figure 3)
Power-on EEPROM restore time (not shown in Figure 3)
Reset EEPROM restore time (not shown in Figure 3)
LOW
HIGH
HD; DAT
SU; DAT
FCL
FDA
RCL
RDA
AD5122A/AD5142A
RCL1
(not shown in Figure 3)
SU; STO
SU; STA
HD; STA
BUF