EVAL-AD5142ADBZ Analog Devices, EVAL-AD5142ADBZ Datasheet - Page 27

• Manufacturer Part Number: EVAL-AD5142ADBZ
• Description: Digital Potentiometer Development Tools EVALUATION BOARD I.C.
• Manufacturer: Analog Devices
• Series: AD5142Ar

Specifications of EVAL-AD5142ADBZ

• Rohs: yes
• Product: Evaluation Boards
• Tool Is For Evaluation Of: AD5142A
• Resistance: 10 kOhms/100 kOhms
• Operating Supply Voltage: 5.5 V
• Interface Type: I2C
• Maximum Operating Temperature: + 125 C
• Factory Pack Quantity: 1

Data Sheet
If the part is configured in linear gain setting mode, the resistance
between Terminal W and Terminal A is directly proportional
to the code loaded in the associate RDAC register. The general
equations for this operation are
AD5122A:
AD5142A:
where:
D is the decimal equivalent of the binary code in the 7-bit/8-bit
RDAC register.
R
R
In the bottom scale condition or top scale condition, a finite
total wiper resistance of 40 Ω is present. Regardless of which
setting the part is operating in, limit the current between
Terminal A to Terminal B, Terminal W to Terminal A, and
Terminal W to Terminal B, to the maximum continuous
current or to the pulse current specified in Table 5. Otherwise,
degradation or possible destruction of the internal switch
contact can occur.
PROGRAMMING THE POTENTIOMETER DIVIDER
Voltage Output Operation
The digital potentiometer easily generates a voltage divider at
wiper-to-B and wiper-to-A that is proportional to the input voltage
at A to B, as shown in Figure 39.
Connecting Terminal A to 5 V and Terminal B to ground
produces an output voltage at the Wiper W to Terminal B
ranging from 0 V to 5 V. The general equation defining the
output voltage at V
input voltage applied to Terminal A and Terminal B is
where:
R
R
Operation of the digital potentiometer in the divider mode
results in a more accurate operation over temperature. Unlike
the rheostat mode, the output voltage is dependent mainly on
the ratio of the internal resistors, R
absolute values. Therefore, the temperature drift reduces to
5 ppm/°C.
AB
W
WB
AW
is the wiper resistance.
(D) can be obtained from Equation 1 and Equation 2.
is the end-to-end resistance.
(D) can be obtained from Equation 3 and Equation 4.
V
R
R
W
AW
AW
(
D
(
(
)
D
D

)
)
Figure 39. Potentiometer Mode Configuration


R
WB
128
R
256
D
D
AB
(
W
D


with respect to ground for any valid
)
V
V
R
R
A
B

AB
AB
V
A



A
B
R
R
R
W
W
AW
R
W
AB
(
AW
D
V
)
and R
OUT

V
From 0x00 to 0x7F (5)
From 0x00 to 0xFF (6)
B
WB
, and not the
Rev. A | Page 27 of 32
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TERMINAL VOLTAGE OPERATING RANGE
The
for protection. These diodes also set the voltage boundary of
the terminal operating voltages. Positive signals present on
Terminal A, Terminal B, or Terminal W that exceed V
clamped by the forward-biased diode. There is no polarity
constraint between V
than V
POWER-UP SEQUENCE
Because there are diodes to limit the voltage compliance at
Terminal A, Terminal B, and Terminal W (see Figure 40), it is
important to power up V
Terminal A, Terminal B, and Terminal W. Otherwise, the diode
is forward-biased such that V
ideal power-up sequence is V
V
inputs is not important as long as they are powered after V
V
ramp rates of the power supplies, once V
power-on preset activates, which restores EEPROM values to
the RDAC registers.
LAYOUT AND POWER SUPPLY BIASING
It is always a good practice to use a compact, minimum lead
length layout design. Ensure that the leads to the input are as
direct as possible with a minimum conductor length. Ground
paths should have low resistance and low inductance. It is also
good practice to bypass the power supplies with quality capacitors.
Apply low equivalent series resistance (ESR) 1 μF to 10 μF
tantalum or electrolytic capacitors at the supplies to minimize
any transient disturbance and to filter low frequency ripple.
Figure 41 illustrates the basic supply bypassing configuration
for the AD5122A/AD5142A.
V
V
DD
SS
A
DD
, V
, and V
AD5122A/AD5142A
B
+
+
, and V
DD
Figure 40. Maximum Terminal Voltages Set by V
C3
10µF
C4
10µF
or lower than V
LOGIC
W
. The order of powering V
. Regardless of the power-up sequence and the
C1
0.1µF
C2
0.1µF
Figure 41. Power Supply Bypassing
A
, V
V
V
are designed with internal ESD diodes
W
DD
AD5122A/
SS
AD5142A
DD
SS
, and V
.
GND
first before applying any voltage to
DD
V
SS
LOGIC
is powered unintentionally. The
, V
DD
B
AD5122A/AD5142A
, but they cannot be higher
, V
0.1µF
LOGIC
C5
DD
A
, V
, digital inputs, and
V
A
W
V
is powered, the
B
DD
SS
B
, V
10µF
DD
C6
W
and V
, and digital
+
DD
SS
V
LOGIC
are
SS
,