EVAL-AD5142ADBZ Analog Devices, EVAL-AD5142ADBZ Datasheet - Page 20

• Manufacturer Part Number: EVAL-AD5142ADBZ
• Description: Digital Potentiometer Development Tools EVALUATION BOARD I.C.
• Manufacturer: Analog Devices
• Series: AD5142Ar

Specifications of EVAL-AD5142ADBZ

• Rohs: yes
• Product: Evaluation Boards
• Tool Is For Evaluation Of: AD5142A
• Resistance: 10 kOhms/100 kOhms
• Operating Supply Voltage: 5.5 V
• Interface Type: I2C
• Maximum Operating Temperature: + 125 C
• Factory Pack Quantity: 1

AD5122A/AD5142A
THEORY OF OPERATION
The
are designed to operate as true variable resistors for analog signals
within the terminal voltage range of V
wiper position is determined by the RDAC register contents. The
RDAC register acts as a scratchpad register that allows unlimited
changes of resistance settings. A secondary register (the input
shift register) can be used to preload the RDAC register data.
The RDAC register can be programmed with any position setting
using the I
this value can be stored in the EEPROM memory. Thereafter,
the wiper position is always restored to that position for subsequent
power-ups. The storing of EEPROM data takes approximately
15 ms; during this time, the device is locked and does not
acknowledge any new command, preventing any changes from
taking place.
RDAC REGISTER AND EEPROM
The RDAC register directly controls the position of the digital
potentiometer wiper. For example, when the RDAC register is
loaded with 0x80 (AD5142A, 256 taps), the wiper is connected
to half scale of the variable resistor. The RDAC register is a standard
logic register; there is no restriction on the number of changes
allowed.
It is possible to both write to and read from the RDAC register
using the digital interface (see Table 10).
The contents of the RDAC register can be stored to the EEPROM
using Command 9 (see Table 10). Thereafter, the RDAC register
always sets at that position for any future on-off-on power
supply sequence. It is possible to read back data saved into the
EEPROM with Command 3 (see Table 10).
Alternatively, the EEPROM can be written to independently
using Command 11 (see Table 16).
INPUT SHIFT REGISTER
For the AD5122A/AD5142A, the input shift register is 16 bits
wide, as shown in Figure 2. The 16-bit word consists of four
control bits, followed by four address bits and by eight data bits.
If the
written to, the lowest data bit (Bit 0) is ignored.
Data is loaded MSB first (Bit 15). The four control bits determine
the function of the software command, as listed in Table 10 and
Table 16.
AD5122A/AD5142A
AD5122A
2
C interface. When a desirable wiper position is found,
RDAC or EEPROM registers are read from or
digital programmable potentiometers
SS
< V
TERM
< V
DD
. The resistor
Rev. A | Page 20 of 32
I
The
interfaces. The device can be connected to an I
device, under the control of a master device. See Figure 3 for a
timing diagram of a typical write sequence.
The
(400 kHz) data transfer modes. Support is not provided for 10-bit
addressing and general call addressing.
The 2-wire serial bus protocol operates as follows:
1.
2.
3.
I
The facility to make hardwired changes to ADDR allows the
user to incorporate up to nine of these devices on one bus as
outlined in Table 9.
Table 9. Device Address Selection
ADDR0 Pin
V
No connect
GND
V
No connect
GND
V
No connect
GND
1
2
2
Not available in bipolar mode (V
LOGIC
LOGIC
LOGIC
C SERIAL DATA INTERFACE
C ADDRESS
AD5122A/AD5142A
AD5122A/AD5142A
The master initiates a data transfer by establishing a start
condition, which is when a high-to-low transition on the
SDA line occurs while SCL is high. The following byte is
the address byte, which consists of the 7-bit slave address
and an R/ W bit. The slave device corresponding to the
transmitted address responds by pulling SDA low during
the ninth clock pulse (this is called the acknowledge bit).
At this stage, all other devices on the bus remain idle while
the selected device waits for data to be written to, or read
from, its shift register.
If the R/ W bit is set high, the master reads from the slave
device. However, if the R/ W bit is set low, the master writes
to the slave device.
Data is transmitted over the serial bus in sequences of nine
clock pulses (eight data bits followed by an acknowledge bit).
The transitions on the SDA line must occur during the low
period of SCL and remain stable during the high period of SCL.
When all data bits have been read from or written to, a stop
condition is established. In write mode, the master pulls the
SDA line high during the tenth clock pulse to establish a stop
condition. In read mode, the master issues a no acknowledge
for the ninth clock pulse (that is, the SDA line remains high).
The master then brings the SDA line low before the tenth
clock pulse, and then high again during the tenth clock pulse
to establish a stop condition.
1
1
1
ADDR1 Pin
V
V
V
No connect
No connect
No connect
GND
GND
GND
LOGIC
LOGIC
LOGIC
SS
have 2-wire, I
supports standard (100 kHz) and fast
< 0 V) or in low voltage mode (V
1
1
1
0100000
0100010
0100011
0101000
0101010
0101011
0101100
0101110
0101111
7-Bit I
2
C-compatible serial
2
C Device Address
Data Sheet
2
C bus as a slave
LOGIC
= 1.8 V).