ATMEGA16U2-16AU Atmel, ATMEGA16U2-16AU Datasheet - Page 293

• Manufacturer Part Number: ATMEGA16U2-16AU
• Description: 8-bit Microcontrollers - MCU 16K Flash
• Manufacturer: Atmel

Specifications of ATMEGA16U2-16AU

• Product Category: 8-bit Microcontrollers - MCU
• Rohs: yes
• Core: AVR
• Data Bus Width: 8 bit
• Program Memory Size: 16 KB
• Data Ram Size: 1.25 KB
• Data Rom Size: 512 B
• Program Memory Type: Flash
• Factory Pack Quantity: 1250

7799D–AVR–11/10
Mnemonics
BREAK
MOVW
SLEEP
SWAP
BSET
BCLR
PUSH
ROR
MOV
WDR
ROL
ASR
SEC
SEN
SEH
LPM
LPM
LPM
SPM
OUT
POP
NOP
BST
BLD
CLC
CLN
SEZ
CLZ
SES
CLS
SEV
CLV
SET
CLT
CLH
LDD
LDD
LDS
STD
STD
STS
SEI
CLI
LDI
LD
LD
LD
LD
LD
LD
LD
LD
LD
ST
ST
ST
ST
ST
ST
ST
ST
ST
IN
Operands
Rd, Z+q
Rd,Y+q
Rd, X+
Rd, - X
Rd, Y+
Rd, - Y
Y+q,Rr
Z+q,Rr
Rd, Rr
Rd, Rr
Rd, Z+
X+, Rr
- X, Rr
Y+, Rr
- Y, Rr
Rd, Z+
Rd, -Z
Z+, Rr
Rd, K
Rd, X
Rd, Y
Rd, Z
-Z, Rr
Rd, Z
Rd, P
Rd, b
Rd, k
X, Rr
Y, Rr
P, Rr
Rr, b
Z, Rr
k, Rr
Rd
Rd
Rd
Rd
Rd
Rr
s
s
DATA TRANSFER INSTRUCTIONS
MCU CONTROL INSTRUCTIONS
Load Program Memory and Post-Inc
Clear Twos Complement Overflow
Set Twos Complement Overflow.
Store Indirect with Displacement
Store Indirect with Displacement
Load Indirect with Displacement
Load Indirect with Displacement
Clear Half Carry Flag in SREG
Set Half Carry Flag in SREG
Rotate Right Through Carry
Bit Store from Register to T
Store Indirect and Post-Inc.
Store Indirect and Pre-Dec.
Store Indirect and Post-Inc.
Store Indirect and Pre-Dec.
Store Indirect and Post-Inc.
Store Indirect and Pre-Dec.
Load Indirect and Post-Inc.
Load Indirect and Pre-Dec.
Load Indirect and Post-Inc.
Load Indirect and Pre-Dec.
Load Indirect and Post-Inc.
Load Indirect and Pre-Dec.
Rotate Left Through Carry
Bit load from T to Register
Move Between Registers
Pop Register from Stack
Global Interrupt Disable
Load Direct from SRAM
Store Program Memory
Push Register on Stack
Global Interrupt Enable
Clear Signed Test Flag
Load Program Memory
Load Program Memory
Store Direct to SRAM
Arithmetic Shift Right
Set Signed Test Flag
Copy Register Word
Clear Negative Flag
Set Negative Flag
Clear T in SREG
Watchdog Reset
Load Immediate
Clear Zero Flag
Set T in SREG
Description
Swap Nibbles
Set Zero Flag
Load Indirect
Load Indirect
Load Indirect
Store Indirect
Store Indirect
Store Indirect
No Operation
Clear Carry
Flag Clear
Set Carry
Flag Set
Out Port
In Port
Break
Sleep
(see specific descr. for Sleep function)
Rd(3..0)Rd(7..4),Rd(7..4)Rd(3..0)
Rd(0)C,Rd(n+1) Rd(n),CRd(7)
Rd(7)C,Rd(n) Rd(n+1),CRd(0)
(see specific descr. for WDR/timer)
Rd(n)  Rd(n+1), n=0..6
ATmega8U2/16U2/32U2
For On-chip Debug Only
Rd  (X), X  X + 1
Rd  (Y), Y  Y + 1
Rd+1:Rd  Rr+1:Rr
X  X - 1, Rd  (X)
Y  Y - 1, Rd  (Y)
Z  Z - 1, Rd  (Z)
(X) Rr, X  X + 1
(Y)  Rr, Y  Y + 1
(Z)  Rr, Z  Z + 1
X  X - 1, (X)  Rr
Y  Y - 1, (Y)  Rr
Rd  (Z), Z  Z+1
Z  Z - 1, (Z)  Rr
Rd  (Z), Z  Z+1
SREG(s)  1
SREG(s)  0
Rd  STACK
STACK  Rr
Rd  (Y + q)
Rd  (Z + q)
Operation
(Y + q)  Rr
(Z + q)  Rr
(Z)  R1:R0
Rd(b)  T
T  Rr(b)
Rd  (X)
Rd  (Y)
Rd  (k)
Rd  (Z)
(Y)  Rr
R0  (Z)
Rd  (Z)
Rd  Rr
Rd  K
(X) Rr
(Z)  Rr
(k)  Rr
Rd  P
P  Rr
C  1
C  0
N  1
N  0
S  1
S  0
V  1
V  0
H  1
H  0
Z  1
Z  0
T  1
T  0
I  1
I 0
SREG(s)
SREG(s)
Z,C,N,V
Z,C,N,V
Z,C,N,V
Flags
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
C
C
N
N
H
H
T
Z
Z
S
S
V
V
T
T
I
I
#Clocks
N/A
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
3
3
3
1
1
2
2
1
1
1
-
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