ATMEGA16U2-16AU Atmel, ATMEGA16U2-16AU Datasheet - Page 292

• Manufacturer Part Number: ATMEGA16U2-16AU
• Description: 8-bit Microcontrollers - MCU 16K Flash
• Manufacturer: Atmel

Specifications of ATMEGA16U2-16AU

• Product Category: 8-bit Microcontrollers - MCU
• Rohs: yes
• Core: AVR
• Data Bus Width: 8 bit
• Program Memory Size: 16 KB
• Data Ram Size: 1.25 KB
• Data Rom Size: 512 B
• Program Memory Type: Flash
• Factory Pack Quantity: 1250

29. Instruction Set Summary
7799D–AVR–11/10
Mnemonics
RCALL
BREQ
BRCC
BRGE
BRHC
ADIW
RJMP
ICALL
CPSE
SBRC
SBRS
BRBS
BRBC
BRNE
BRCS
BRSH
BRLO
BRPL
BRHS
BRTS
BRTC
BRVS
BRVC
SBIW
CALL
BRMI
BRLT
SUBI
SBCI
ANDI
COM
IJMP
RETI
SBIC
SBIS
BRIE
BRID
ADD
ADC
SUB
SBC
AND
EOR
NEG
SBR
CBR
DEC
SER
CPC
TST
CLR
JMP
RET
LSR
ORI
INC
CPI
SBI
CBI
LSL
OR
CP
Operands
Rd, Rr
Rd, Rr
Rd, Rr
Rd, Rr
Rd, Rr
Rd, Rr
Rd, Rr
Rdl,K
Rd, K
Rd, K
Rdl,K
Rd, K
Rd, K
Rd,Rr
Rd,Rr
Rd,Rr
Rd,K
Rd,K
Rd,K
Rr, b
Rr, b
P, b
P, b
s, k
s, k
P,b
P,b
Rd
Rd
Rd
Rd
Rd
Rd
Rd
Rd
Rd
k
k
k
k
k
k
k
k
k
k
k
k
k
k
k
k
k
k
k
k
k
k
ARITHMETIC AND LOGIC INSTRUCTIONS
BIT AND BIT-TEST INSTRUCTIONS
BRANCH INSTRUCTIONS
Subtract with Carry Constant from Reg.
Logical AND Register and Constant
Branch if Greater or Equal, Signed
Logical OR Register and Constant
Compare Register with Immediate
Branch if Overflow Flag is Cleared
Branch if Less Than Zero, Signed
Subtract with Carry two Registers
Branch if Half Carry Flag Cleared
Skip if Bit in I/O Register Cleared
Subtract Constant from Register
Subtract Immediate from Word
Skip if Bit in I/O Register is Set
Branch if Status Flag Cleared
Branch if Overflow Flag is Set
Add with Carry two Registers
Skip if Bit in Register Cleared
Branch if Half Carry Flag Set
Branch if Interrupt Disabled
Skip if Bit in Register is Set
Branch if Interrupt Enabled
Branch if Same or Higher
Branch if Status Flag Set
Relative Subroutine Call
Branch if T Flag Cleared
Add Immediate to Word
Exclusive OR Registers
Clear Bit in I/O Register
Branch if Carry Cleared
Compare, Skip if Equal
Subtract two Registers
Logical AND Registers
Clear Bit(s) in Register
Test for Zero or Minus
Direct Subroutine Call
Set Bit in I/O Register
Logical OR Registers
Set Bit(s) in Register
Compare with Carry
Branch if T Flag Set
One’s Complement
Two’s Complement
Indirect Jump to (Z)
Branch if Not Equal
Branch if Carry Set
Add two Registers
Indirect Call to (Z)
Subroutine Return
Logical Shift Right
Logical Shift Left
Interrupt Return
Branch if Lower
Branch if Equal
Branch if Minus
Description
Clear Register
Relative Jump
Branch if Plus
Set Register
Direct Jump
Decrement
Increment
Compare
if (SREG(s) = 1) then PCPC+k + 1
if (SREG(s) = 0) then PCPC+k + 1
if (N  V= 0) then PC  PC + k + 1
if (N  V= 1) then PC  PC + k + 1
if (C = 1) then PC  PC + k + 1
if (C = 0) then PC  PC + k + 1
if (C = 0) then PC  PC + k + 1
if (C = 1) then PC  PC + k + 1
if (N = 1) then PC  PC + k + 1
if (N = 0) then PC  PC + k + 1
if (H = 1) then PC  PC + k + 1
if (H = 0) then PC  PC + k + 1
if (T = 1) then PC  PC + k + 1
if (Z = 1) then PC  PC + k + 1
if (Z = 0) then PC  PC + k + 1
if (T = 0) then PC  PC + k + 1
if (V = 1) then PC  PC + k + 1
if (V = 0) then PC  PC + k + 1
if ( I = 1) then PC  PC + k + 1
if ( I = 0) then PC  PC + k + 1
if (Rd = Rr) PC PC + 2 or 3
if (Rr(b)=0) PC  PC + 2 or 3
if (Rr(b)=1) PC  PC + 2 or 3
Rd(n+1)  Rd(n), Rd(0)  0
Rd(n)  Rd(n+1), Rd(7)  0
if (P(b)=0) PC  PC + 2 or 3
if (P(b)=1) PC  PC + 2 or 3
ATmega8U2/16U2/32U2
Rdh:Rdl  Rdh:Rdl + K
Rdh:Rdl  Rdh:Rdl - K
Rd  Rd  (0xFF - K)
Rd  Rd + Rr + C
PC PC + k + 1
Rd  Rd - Rr - C
Rd  0xFF  Rd
PC  PC + k + 1
Rd  0x00  Rd
Rd  Rd - K - C
Rd  Rd  Rd
Rd  Rd + Rr
Rd  Rd  Rr
Rd  Rd  Rd
Rd Rd  Rr
Rd  Rd v Rr
PC  STACK
PC  STACK
Rd  Rd - Rr
Rd  Rd K
Rd Rd v K
Rd  Rd v K
Rd  Rd + 1
Rd  Rd  1
Operation
Rd  Rd - K
I/O(P,b)  1
I/O(P,b)  0
Rd  Rr  C
Rd  0xFF
PC  Z
PC  Z
PC k
PC  k
Rd  Rr
Rd  K
Z, N,V,C,H
Z, N,V,C,H
Z, N,V,C,H
Z,C,N,V,H
Z,C,N,V,H
Z,C,N,V,S
Z,C,N,V,H
Z,C,N,V,H
Z,C,N,V,H
Z,C,N,V,H
Z,C,N,V,S
Z,C,N,V,H
Z,C,N,V
Z,C,N,V
Z,C,N,V
Flags
Z,N,V
Z,N,V
Z,N,V
Z,N,V
Z,N,V
Z,N,V
Z,N,V
Z,N,V
Z,N,V
Z,N,V
Z,N,V
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
I
#Clocks
1/2/3
1/2/3
1/2/3
1/2/3
1/2/3
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1
1
2
1
1
1
1
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
3
4
4
5
5
5
1
1
1
2
2
1
1
292