P83C654X2FBD/CV710 NXP Semiconductors, P83C654X2FBD/CV710 Datasheet - Page 47

• Manufacturer Part Number: P83C654X2FBD/CV710
• Description: 8-bit Microcontrollers - MCU P83C654X2FBD/LQFP44/TRAYBM//CV
• Manufacturer: NXP Semiconductors

Specifications of P83C654X2FBD/CV710

• Core: 80C51
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 16 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 256 B
• Operating Supply Voltage: 5 V
• Package / Case: SOT-187-2
• Mounting Style: SMD/SMT
• Interface Type: I2C, Serial
• Number Of Programmable I/os: 4
• Number Of Timers: 3
• Processor Series: 80C51
• Program Memory Type: OTP EPROM

Philips Semiconductors
Table 13.
Slave Transmitter Mode: In the slave transmitter mode, a number
of data bytes are transmitted to a master receiver (see Figure 31).
Data transfer is initialized as in the slave receiver mode. When
S1ADR and S1CON have been initialized, I
addressed by its own slave address followed by the data direction
bit which must be logic 1 (R) for the I
transmitter mode. After its own slave address and the R bit have
been received, the serial interrupt flag (SI) is set and a valid status
code can be read from S1STA. This status code is used to vector to
an interrupt service routine, and the appropriate action to be taken
for each of these status codes is detailed in Table 12. The slave
transmitter mode may also be entered if arbitration is lost while I
is in the master mode (see state B0H).
If the AA bit is reset during a transfer, I
of the transfer and enter state C0H or C8H. I
not addressed slave mode and will ignore the master receiver if it
continues the transfer. Thus the master receiver receives all 1s as
serial data. While AA is reset, I
address or a general call address. However, the I
monitored, and address recognition may be resumed at any time by
setting AA. This means that the AA bit may be used to temporarily
isolate I
Miscellaneous States: There are two S1STA codes that do not
correspond to a defined I
are discussed below.
S1STA = F8H:
This status code indicates that no relevant information is available
because the serial interrupt flag, SI, is not yet set. This occurs
between other states and when I
transfer.
S1STA = 00H:
This status code indicates that a bus error has occurred during an
I
condition occurs at an illegal position in the format frame. Examples
of such illegal positions are during the serial transfer of an address
byte, a data byte, or an acknowledge bit. A bus error may also be
caused when external interference disturbs the internal I
When a bus error occurs, SI is set. To recover from a bus error, the
STO flag must be set and SI must be cleared. This causes I
enter the “not addressed” slave mode (a defined state) and to clear
2004 Apr 20
2
STATUS
STATUS
(S1STA)
(S1STA)
C serial transfer. A bus error is caused when a START or STOP
F8H
00H
CODE
80C51 8-bit microcontroller family
256B RAM, low voltage (2.7 to 5.5 V), low power, high speed
(30/33 MHz)
2
C from the I
information available;
No relevant state
SI = 0
Bus error during MST
or selected slave
modes, due to an
illegal START or
STOP condition. State
00H can also occur
when interference
causes I
an undefined state.
STATUS OF THE
STATUS OF THE
Miscellaneous States
I
HARDWARE
HARDWARE
2
C BUS AND
2
2
C-bus.
C to enter
2
C hardware state (see Table 13). These
2
C does not respond to its own slave
2
C is not involved in a serial
2
No S1DAT action
No S1DAT action
C to operate in the slave
TO/FROM S1DAT
TO/FROM S1DAT
2
C will transmit the last byte
APPLICATION SOFTWARE RESPONSE
2
C waits until it is
2
C is switched to the
16 kB OTP/ROM,
2
C-bus is still
2
C signals.
2
STA
C to
0
No S1CON action
2
C
TO S1CON
STO
1
47
the STO flag (no other bits in S1CON are affected). The SDA and
SCL lines are released (a STOP condition is not transmitted).
Some Special Cases: The I
following special cases that may occur during a serial transfer:
Simultaneous Repeated START Conditions from Two Masters
A repeated START condition may be generated in the master
transmitter or master receiver modes. A special case occurs if
another master simultaneously generates a repeated START
condition (see Figure 32). Until this occurs, arbitration is not lost by
either master since they were both transmitting the same data.
If the I
I
release the bus, and no interrupt request is generated. If another
master frees the bus by generating a STOP condition, I
transmit a normal START condition (state 08H), and a retry of the
total serial data transfer can commence.
D
Arbitration may be lost in the master transmitter and master receiver
modes (see Figure 24). Loss of arbitration is indicated by the
following states in S1STA; 38H, 68H, 78H, and B0H (see Figures 28
and 29).
If the STA flag in S1CON is set by the routines which service these
states, then, if the bus is free again, a START condition (state 08H)
is transmitted without intervention by the CPU, and a retry of the
total serial transfer can commence.
F
In some applications, it may be possible for an uncontrolled source
to cause a bus hang-up. In such situations, the problem may be
caused by interference, temporary interruption of the bus or a
temporary short-circuit between SDA and SCL.
If an uncontrolled source generates a superfluous START or masks
a STOP condition, then the I
STA flag is set and bus access is not obtained within a reasonable
amount of time, then a forced access to the I
is achieved by setting the STO flag while the STA flag is still set. No
STOP condition is transmitted. The I
STOP condition was received and is able to transmit a START
condition. The STO flag is cleared by hardware (see Figure 33).
SI
2
0
ORCED
C-bus before generating a repeated START condition itself, it will
ATA
T
2
AA
RANSFER
C hardware detects a repeated START condition on the
X
A
CCESS TO THE
Wait or proceed current transfer
Only the internal hardware is affected in the MST or
addressed SLV modes. In all cases, the bus is
released and I
SLV mode. STO is reset.
A
NEXT ACTION TAKEN BY I
FTER
P83C654X2/P87C654X2
L
I
OSS OF
2
C
-BUS
2
C is switched to the not addressed
2
2
C-bus stays busy indefinitely. If the
C hardware has facilities to handle the
A
RBITRATION
2
C hardware behaves as if a
2
C-bus is possible. This
2
2
C HARDWARE
2
Product data
C will