P83C654X2FBD/CV710 NXP Semiconductors, P83C654X2FBD/CV710 Datasheet - Page 38

• Manufacturer Part Number: P83C654X2FBD/CV710
• Description: 8-bit Microcontrollers - MCU P83C654X2FBD/LQFP44/TRAYBM//CV
• Manufacturer: NXP Semiconductors

Specifications of P83C654X2FBD/CV710

• Core: 80C51
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 16 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 256 B
• Operating Supply Voltage: 5 V
• Package / Case: SOT-187-2
• Mounting Style: SMD/SMT
• Interface Type: I2C, Serial
• Number Of Programmable I/os: 4
• Number Of Timers: 3
• Processor Series: 80C51
• Program Memory Type: OTP EPROM

Philips Semiconductors
More Information on I
modes are:
– Master Transmitter
– Master Receiver
– Slave Receiver
– Slave Transmitter
Data transfers in each mode of operation are shown in Figures
28–31. These figures contain the following abbreviations:
Abbreviation
S
SLA
R
W
A
A
Data
P
In Figures 28-31, circles are used to indicate when the serial
interrupt flag is set. The numbers in the circles show the status code
held in the S1STA register. At these points, a service routine must
be executed to continue or complete the serial transfer. These
service routines are not critical since the serial transfer is suspended
until the serial interrupt flag is cleared by software.
When a serial interrupt routine is entered, the status code in S1STA
is used to branch to the appropriate service routine. For each status
code, the required software action and details of the following serial
transfer are given in Tables 9-13.
Master Transmitter Mode: In the master transmitter mode, a
number of data bytes are transmitted to a slave receiver (see
Figure 28). Before the master transmitter mode can be entered,
S1CON must be initialized as follows:
S1CON
(D8H)
CR0, CR1, and CR2 define the serial bit rate. ENS1 must be set to
logic 1 to enable I
its own slave address or the general call address in the event of
another device becoming master of the bus. In other words, if AA is
reset, SIO0 cannot enter a slave mode. STA, STO, and SI must be
reset.
The master transmitter mode may now be entered by setting the
STA bit using the SETB instruction. The I
I
free. When a START condition is transmitted, the serial interrupt flag
(SI) is set, and the status code in the status register (S1STA) will be
08H. This status code must be used to vector to an interrupt service
routine that loads S1DAT with the slave address and the data
direction bit (SLA+W). The SI bit in S1CON must then be reset
before the serial transfer can continue.
When the slave address and the direction bit have been transmitted
and an acknowledgment bit has been received, the serial interrupt
flag (SI) is set again, and a number of status codes in S1STA are
possible. There are 18H, 20H, or 38H for the master mode and also
68H, 78H, or B0H if the slave mode was enabled (AA = logic 1). The
appropriate action to be taken for each of these status codes is
detailed in Table 9. After a repeated start condition (state 10H). I
2004 Apr 20
2
C-bus and generate a start condition as soon as the bus becomes
80C51 8-bit microcontroller family
256B RAM, low voltage (2.7 to 5.5 V), low power, high speed
(30/33 MHz)
rate
CR2
bit
7
Start condition
7-bit slave address
Read bit (HIGH level at SDA)
Write bit (low level at SDA)
Acknowledge bit (low level at SDA)
Not acknowledge bit (HIGH level at SDA)
8-bit data byte
Stop condition
2
C. If the AA bit is reset, I
ENS1
6
1
2
C Operating Modes: The four operating
Explanation
STA
5
0
STO
4
0
2
C logic will now test the
2
C will not acknowledge
SI
0
3
16 kB OTP/ROM,
AA
X
2
CR1
1
bit rate
CR0
0
2
C
38
may switch to the master receiver mode by loading S1DAT with
SLA+R).
Master Receiver Mode: In the master receiver mode, a number of
data bytes are received from a slave transmitter (see Figure 29).
The transfer is initialized as in the master transmitter mode. When
the start condition has been transmitted, the interrupt service routine
must load S1DAT with the 7-bit slave address and the data direction
bit (SLA+R). The SI bit in S1CON must then be cleared before the
serial transfer can continue.
When the slave address and the data direction bit have been
transmitted and an acknowledgment bit has been received, the
serial interrupt flag (SI) is set again, and a number of status codes in
S1STA are possible. These are 40H, 48H, or 38H for the master
mode and also 68H, 78H, or B0H if the slave mode was enabled
(AA = logic 1). The appropriate action to be taken for each of these
status codes is detailed in Table 10. ENS1, CR1, and CR0 are not
affected by the serial transfer and are not referred to in Table 10.
After a repeated start condition (state 10H), I
master transmitter mode by loading S1DAT with SLA+W.
Slave Receiver Mode: In the slave receiver mode, a number of
data bytes are received from a master transmitter (see Figure 30).
To initiate the slave receiver mode, S1ADR and S1CON must be
loaded as follows:
The upper 7 bits are the address to which I
addressed by a master. If the LSB (GC) is set, I
the general call address (00H); otherwise it ignores the general call
address.
S1CON
(D8H)
CR0, CR1, and CR2 do not affect I
be set to logic 1 to enable I
to acknowledge its own slave address or the general call address.
STA, STO, and SI must be reset.
When S1ADR and S1CON have been initialized, I
addressed by its own slave address followed by the data direction
bit which must be logic 0 (W) for I
mode. After its own slave address and the W bit have been
received, the serial interrupt flag (I) is set and a valid status code
can be read from S1STA. This status code is used to vector to an
interrupt service routine, and the appropriate action to be taken for
each of these status codes is detailed in Table 11. The slave
receiver mode may also be entered if arbitration is lost while I
in the master mode (see status 68H and 78H).
If the AA bit is reset during a transfer, I
acknowledge (logic 1) to SDA after the next received data byte.
While AA is reset, I
a general call address. However, the I
address recognition may be resumed at any time by setting AA. This
means that the AA bit may be used to temporarily isolate I
the I
AUXR#
2
C-bus.
Auxiliary
CR2
7
X
2
8EH
C does not respond to its own slave address or
ENS1
P83C654X2/P87C654X2
1
6
–
2
C. The AA bit must be set to enable I
STA
5
0
–
2
C to operate in the slave receiver
2
C in the slave mode. ENS1 must
STO
–
4
2
0
2
C-bus is still monitored and
C will return a not
–
2
C will respond when
SI
0
2
3
C may switch to the
Fast/
Std
I
2
2
C
C will respond to
AA
2
2
1
C waits until it is
–
CR1
Product data
X
1
2
C from
–
2
C is
CR0
0
X
AO
2
C