C8051F510-IMR Silicon Labs, C8051F510-IMR Datasheet - Page 94
C8051F510-IMR
Manufacturer Part Number
C8051F510-IMR
Description
8-bit Microcontrollers - MCU 50 MIPS 32 kB 4 kB CAN2.0 LIN 2.1 SPI
Manufacturer
Silicon Labs
Datasheet
1.C8051F510-IMR.pdf
(312 pages)
Specifications of C8051F510-IMR
Rohs
yes
Core
8051
Data Bus Width
8 bit
Processor Series
C8051
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C8051F50x/F51x
SFR Definition 11.3. SP: Stack Pointer
SFR Address = 0x81; SFR Page = All Pages
SFR Definition 11.4. ACC: Accumulator
SFR Address = 0xE0; SFR Page = All Pages; Bit-Addressable
SFR Definition 11.5. B: B Register
SFR Address = 0xF0; SFR Page = All Pages; Bit-Addressable
94
Name
Reset
Name
Reset
Name
Reset
7:0
7:0
7:0
Bit
Bit
Bit
Type
Type
Type
Bit
Bit
Bit
ACC[7:0]
SP[7:0]
Name
Name
Name
B[7:0]
7
0
7
0
7
0
Stack Pointer.
The Stack Pointer holds the location of the top of the stack. The stack pointer is incre-
mented before every PUSH operation. The SP register defaults to 0x07 after reset.
Accumulator.
This register is the accumulator for arithmetic operations.
B Register.
This register serves as a second accumulator for certain arithmetic operations.
6
0
6
0
6
0
5
0
5
0
5
0
Rev. 1.2
4
0
4
0
4
0
ACC[7:0]
SP[7:0]
B[7:0]
R/W
R/W
R/W
Function
Function
Function
3
0
3
0
3
0
2
1
2
0
2
0
1
1
1
0
1
0
0
1
0
0
0
0
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