C8051F510-IMR Silicon Labs, C8051F510-IMR Datasheet - Page 166
C8051F510-IMR
Manufacturer Part Number
C8051F510-IMR
Description
8-bit Microcontrollers - MCU 50 MIPS 32 kB 4 kB CAN2.0 LIN 2.1 SPI
Manufacturer
Silicon Labs
Datasheet
1.C8051F510-IMR.pdf
(312 pages)
Specifications of C8051F510-IMR
Rohs
yes
Core
8051
Data Bus Width
8 bit
Processor Series
C8051
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C8051F50x/F51x
SFR Definition 19.1. CLKSEL: Clock Select
SFR Address = 0x8F; SFR Page = 0x0F;
Important Note: If the selected system clock is greater than 25 MHz, please be aware of the following:
166
Name
Reset
7:2
1:0
Bit
Type
Bit
Flash Scale Timing must be configured for the faster system clock. See SFR Definition 15.3 for more
details.
VDD and VDDA voltage must be 2 V or higher.
It is recommended to enable the VDD monitor as a reset source and configure it for the high threshold.
See SFR Definition 17.1 for details on configuring the VDD monitor. If the VDD monitor is configured to
the high threshold, the VDD and VDDA voltage must be greater than the VDD monitor high threshold.
See Table 5.4 for VDD monitor threshold specifications.
CLKSL[1:0] System Clock Source Select Bits.
Unused
Name
R
7
0
Read = 000000b; Write = Don’t Care
00: SYSCLK derived from the Internal Oscillator and scaled per the IFCN bits in reg-
ister OSCICN.
01: SYSCLK derived from the External Oscillator circuit.
10: SYSCLK derived from the Clock Multiplier.
11: reserved.
R
6
0
R
5
0
Rev. 1.2
R
4
0
Function
R
3
0
R
2
0
1
0
CLKSL[1:0]
R/W
0
0
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