C8051F510-IMR Silicon Labs, C8051F510-IMR Datasheet - Page 65
C8051F510-IMR
Manufacturer Part Number
C8051F510-IMR
Description
8-bit Microcontrollers - MCU 50 MIPS 32 kB 4 kB CAN2.0 LIN 2.1 SPI
Manufacturer
Silicon Labs
Datasheet
1.C8051F510-IMR.pdf
(312 pages)
Specifications of C8051F510-IMR
Rohs
yes
Core
8051
Data Bus Width
8 bit
Processor Series
C8051
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SFR Definition 6.7. ADC0CN: ADC0 Control
SFR Address = 0xE8; SFR Page = 0x00; Bit-Addressable
Reset
Name
Bit
1:0 AD0CM[1:0] ADC0 Start of Conversion Mode Select.
Type
7
6
5
4
3
2
Bit
BURSTEN ADC0 Burst Mode Enable Bit.
AD0BUSY ADC0 Busy Bit.
AD0WINT
AD0LJST
AD0INT
AD0EN
Name
AD0EN
R/W
7
0
ADC0 Enable Bit.
0: ADC0 Disabled. ADC0 is in low-power shutdown.
1: ADC0 Enabled. ADC0 is active and ready for data conversions.
0: Burst Mode Disabled.
1: Burst Mode Enabled.
ADC0 Conversion Complete Interrupt Flag.
0: ADC0 has not completed a data conversion since AD0INT was last cleared.
1: ADC0 has completed a data conversion.
ADC0 Window Compare Interrupt Flag.
This bit must be cleared by software
0: ADC0 Window Comparison Data match has not occurred since this flag was last
cleared.
1: ADC0 Window Comparison Data match has occurred.
ADC0 Left Justify Select Bit.
0: Data in ADC0H:ADC0L registers is right-justified
1: Data in ADC0H:ADC0L registers is left-justified. This option should not be used
with a repeat count greater than 1 (when AD0RPT[1:0] is 01b, 10b, or 11b).
00: ADC0 start-of-conversion source is write of 1 to AD0BUSY.
01: ADC0 start-of-conversion source is overflow of Timer 1.
10: ADC0 start-of-conversion source is rising edge of external CNVSTR.
11: ADC0 start-of-conversion source is overflow of Timer 2.
BURSTEN
R/W
0
6
AD0INT
R/W
5
0
AD0BUSY AD0WINT AD0LJST
R/W
Rev. 1.2
Read:
0: ADC0 conversion is not
in progress.
1: ADC0 conversion is in
progress.
4
0
Function
R/W
3
0
C8051F50x/F51x
R/W
2
0
Write:
0: No Effect.
1: Initiates ADC0 Conver-
sion if AD0CM[1 : 0] = 00b
1
0
AD0CM[1:0]
R/W
0
0
65
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