IS42S32800B-7BL ISSI, Integrated Silicon Solution Inc, IS42S32800B-7BL Datasheet - Page 9
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IS42S32800B-7BL
Manufacturer Part Number
IS42S32800B-7BL
Description
IC SDRAM 256MBIT 143MHZ 90BGA
Manufacturer
ISSI, Integrated Silicon Solution Inc
Type
SDRAMr
Datasheet
1.IS42S32800B-7BL.pdf
(62 pages)
Specifications of IS42S32800B-7BL
Package / Case
90-BGA
Memory Size
256M (8Mx32)
Format - Memory
RAM
Memory Type
SDRAM
Speed
143MHz
Interface
Parallel
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
0°C ~ 70°C
Data Bus Width
32 bit
Organization
2 Mbit x 32
Maximum Clock Frequency
143 MHz
Access Time
7 ns
Supply Voltage (max)
3.6 V
Supply Voltage (min)
3 V
Maximum Operating Current
150 mA
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Density
256Mb
Address Bus
14b
Access Time (max)
5.5ns
Maximum Clock Rate
143MHz
Operating Supply Voltage (typ)
3.3V
Package Type
BGA
Operating Temp Range
0C to 70C
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
Supply Current
150mA
Pin Count
90
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
706-1024
Available stocks
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The read data appears on the DQs subject to the values on the DQM inputs two clocks earlier (i.e.DQM latency is two clocks
for output buffers). A read burst without the auto precharge function may be interrupted by a subsequent Read or Write
command to the same bank or the other active bank before the end of the burst length.It may be interrupted by a
BankPrecharge/PrechargeAll command to the same bank too.The interrupt coming from the Read command can occur on
any clock cycle following a previous Read command (refer to the following figure).
The DQM inputs are used to avoid I/O contention on the DQ pins when the interrupt comes from a Write command.The
DQMs must be asserted (HIGH)at least two clocks prior to the Write command to suppress data-out on the DQ pins.To
guarantee the DQ pins against I/O contention,a single cycle with high-impedance on the DQ pins must occur between the
last read data and the Write command (refer to the following three figures).If the data output of the burst read occurs at the
second clock of the burst write,the DQMs must be asserted (HIGH)at least one clock prior to the Write command to avoid
internal bus contention.
IS42S32800B
Integrated Silicon Solution, Inc.
Rev. F
07/21/09
CAS# latency=2
t CK2 , DQ s
CLK
COMMAND
CAS# latency=3
t CK3 , DQ s
CAS# latency=2
t CK2 , DQ s
CLK
COMMAND
CAS# latency=3
t CK3 , DQ s
Read Interrupted by a Read (Burst Length =4,CAS#Latency =2,3)
READ A
Burst Read Operation(Burst Length =4,CAS#Latency =2,3)
T0
READ A
T0
NOP
READ B
T1
T1
T2
DOUT A 0
NOP
DOUT A 0
T2
NOP
DOUT A 1
NOP
T3
DOUT A 0
DOUT B 0
NOP
T3
DOUT A 0
DOUT A 1
DOUT A 2
T4
NOP
DOUT B 0
T4
NOP
DOUT B 1
DOUT A 3
T5
DOUT A 2
NOP
NOP
DOUT B 2
T5
DOUT B 1
DOUT A 3
T6
NOP
NOP
T6
DOUT B 3
DOUT B
2
T7
T7
NOP
NOP
DOUT B 3
NOP
T8
NOP
T8
9