IS42S32800B-7BL ISSI, Integrated Silicon Solution Inc, IS42S32800B-7BL Datasheet - Page 13

• Manufacturer Part Number: IS42S32800B-7BL
• Description: IC SDRAM 256MBIT 143MHZ 90BGA
• Manufacturer: ISSI, Integrated Silicon Solution Inc
• Type: SDRAMr

Specifications of IS42S32800B-7BL

• Package / Case: 90-BGA
• Memory Size: 256M (8Mx32)
• Format - Memory: RAM
• Memory Type: SDRAM
• Speed: 143MHz
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Data Bus Width: 32 bit
• Organization: 2 Mbit x 32
• Maximum Clock Frequency: 143 MHz
• Access Time: 7 ns
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Maximum Operating Current: 150 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Density: 256Mb
• Address Bus: 14b
• Access Time (max): 5.5ns
• Maximum Clock Rate: 143MHz
• Operating Supply Voltage (typ): 3.3V
• Package Type: BGA
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Supply Current: 150mA
• Pin Count: 90
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 706-1024

IS42S32800B
6
Integrated Silicon Solution, Inc.
Rev. F
07/21/09
Concurrent Auto Precharge
An access command (READ or WRITE) to another bank while an access command with auto precharge enabled
is executing is not allowed by SDRAMs, unless the SDRAM supports CONCURRENT AUTO PRECHARGE.
ICSI SDRAMs support CONCURRENT AUTO PRECHARGE. Four cases where CONCURRENT AUTO
PRECHARGE occurs are defined below.
READ with Auto Precharge
· Interrupted by a READ (with or without auto precharge): A READ to bank m will interrupt a READ on bank n,
· Interrupted by a WRITE (with or without auto precharge): A WRITE to bank m will interrupt a READ on bank n
CAS latency later. The PRECHARGE to bank n will begin when the READ to bank m is regis-tered.
when registered. DQM should be used two clocks prior to the WRITE command to prevent bus contention. The
PRECHARGE to bank n will begin when the WRITE to bank m is registered.
Internal
States
Internal
States
NOTE: 1. DQM is HIGH at T2 to prevent D
NOTE: DQM is LOW.
READ With Auto Precharge Interrupted by a WRITE
READ With Auto Precharge Interrupted by a READ
COMMAND
ADDRESS
BANK m
COMMAND
BANK n
ADDRESS
BANK m
BANK n
CLK
DQM
DQ
CLK
DQ
1
Active
Page
READ - AP
BANK n,
Page Active
T0
BANK n
NOP
COL a
T0
READ with Burst of 4
CAS Latency = 3 (BANK n)
READ - AP
Page Active
BANK n,
Page Active
T1
BANK n
NOP
COL a
T1
OUT
READ with Burst of 4
CAS Latency = 3 (BANK n)
-a+1 from contending with D
T2
NOP
T2
NOP
T3
D
NOP
OUT
a
BANK m,
READ - AP
T3
BANK m
COL d
Interrupt Burst, Precharge
CAS Latency = 3 (BANK m)
READ with Burst of 4
BANK m,
WRITE - AP
COL d
BANK m
T4
D
d
IN
IN
Interrupt Burst, Precharge
WRITE with Burst of 4
-d at T4.
T4
NOP
D
T5
OUT
a
t
d + 1
RP - BANK n
NOP
D
IN
t
RP - BANK n
T5
NOP
T6
D
a + 1
d + 2
NOP
D
OUT
IN
DON’T CARE
T6
NOP
T7
t WR - BANK m
d + 3
NOP
D
D
IN
OUT
Write-Back
d
Idle
DON T CARE
Idle
T7
NOP
t RP - BANK m
Precharge
D
d + 1
OUT
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