MT48LC2M32B2TG-7:G TR Micron Technology Inc, MT48LC2M32B2TG-7:G TR Datasheet - Page 59
![IC SDRAM 64MBIT 143MHZ 86TSOP](/photos/7/22/72264/557-86-tsop_sml.jpg)
MT48LC2M32B2TG-7:G TR
Manufacturer Part Number
MT48LC2M32B2TG-7:G TR
Description
IC SDRAM 64MBIT 143MHZ 86TSOP
Manufacturer
Micron Technology Inc
Type
SDRAMr
Datasheet
1.MT48LC2M32B2P-6G_TR.pdf
(69 pages)
Specifications of MT48LC2M32B2TG-7:G TR
Format - Memory
RAM
Memory Type
SDRAM
Memory Size
64M (2Mx32)
Speed
143MHz
Interface
Parallel
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
0°C ~ 70°C
Package / Case
86-TSOP
Package
86TSOP-II
Density
64 Mb
Address Bus Width
13 Bit
Operating Supply Voltage
3.3 V
Maximum Clock Rate
143 MHz
Maximum Random Access Time
17|8|5.5 ns
Organization
2Mx32
Address Bus
13b
Access Time (max)
17/8/5.5ns
Operating Supply Voltage (typ)
3.3V
Package Type
TSOP-II
Operating Temp Range
0C to 70C
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
Supply Current
160mA
Pin Count
86
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
557-1076-2
Figure 41:
PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5
64MSDRAMx32_2.fm - Rev. J 12/08 EN
COMMAND
BA0, BA1
DQM 0-3
A0-A9
CLK
CKE
A10
DQ
t CMS
t CKS
t AS
t AS
t AS
Alternating Bank Read Accesses
ACTIVE
BANK 0
T0
ROW
ROW
t CKH
t CMH
t AH
t AH
t AH
Notes:
t RCD - BANK 0
t RAS - BANK 0
t
t
RC - BANK 0
RRD
t CK
T1
NOP
1. For this example, BL = 4 and CL = 2.
2. A8 and A9 = “Don’t Care.”
ENABLE AUTO PRECHARGE
t CMS
t CL
COLUMN m 2
BANK 0
T2
READ
t CMH
t CH
CAS Latency - BANK 0
T3
NOP
t LZ
t AC
59
BANK 4
ACTIVE
T4
ROW
ROW
D
OUT
t OH
t AC
m
t RCD - BANK 4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
D
T5
OUT
NOP
m + 1
t OH
t AC
ENABLE AUTO PRECHARGE
COLUMN b 2
BANK 4
D
T6
READ
OUT
m + 2
t OH
t AC
CAS Latency - BANK 4
t RP - BANK 0
©2001 Micron Technology, Inc. All rights reserved.
D
T7
OUT
NOP
64Mb: x32 SDRAM
m + 3
t OH
Timing Diagrams
t AC
BANK 0
T8
ROW
ACTIVE
ROW
DON’T CARE
UNDEFINED
D
OUT
t RCD - BANK 0
t OH
t AC
b