MT48LC2M32B2TG-7:G TR Micron Technology Inc, MT48LC2M32B2TG-7:G TR Datasheet - Page 2
![IC SDRAM 64MBIT 143MHZ 86TSOP](/photos/7/22/72264/557-86-tsop_sml.jpg)
MT48LC2M32B2TG-7:G TR
Manufacturer Part Number
MT48LC2M32B2TG-7:G TR
Description
IC SDRAM 64MBIT 143MHZ 86TSOP
Manufacturer
Micron Technology Inc
Type
SDRAMr
Datasheet
1.MT48LC2M32B2P-6G_TR.pdf
(69 pages)
Specifications of MT48LC2M32B2TG-7:G TR
Format - Memory
RAM
Memory Type
SDRAM
Memory Size
64M (2Mx32)
Speed
143MHz
Interface
Parallel
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
0°C ~ 70°C
Package / Case
86-TSOP
Package
86TSOP-II
Density
64 Mb
Address Bus Width
13 Bit
Operating Supply Voltage
3.3 V
Maximum Clock Rate
143 MHz
Maximum Random Access Time
17|8|5.5 ns
Organization
2Mx32
Address Bus
13b
Access Time (max)
17/8/5.5ns
Operating Supply Voltage (typ)
3.3V
Package Type
TSOP-II
Operating Temp Range
0C to 70C
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
Supply Current
160mA
Pin Count
86
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
557-1076-2
General Description
Automotive Temperature
PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5
64MSDRAMx32_1.fm - Rev. J 12/08 EN
The Micron
containing 67,108,864 bits. It is internally configured as a quad-bank DRAM with a
synchronous interface (all signals are registered on the positive edge of the clock signal,
CLK). Each of the 16,777,216-bit banks is organized as 2,048 rows by 256 columns by 32
bits.
Read and write accesses to the SDRAM are burst oriented; accesses start at a selected
location and continue for a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an ACTIVE command, which is then
followed by a READ or WRITE command. The address bits registered coincident with the
ACTIVE command are used to select the bank and row to be accessed (BA0, BA1 select
the bank, A0–A10 select the row). The address bits registered coincident with the READ
or WRITE command are used to select the starting column location for the burst access.
The SDRAM provides for programmable read or write burst lengths (BL) of 1, 2, 4, or 8
locations, or the full page, with a burst terminate option. An auto precharge function
may be enabled to provide a self-timed row precharge that is initiated at the end of the
burst sequence.
The 64Mb SDRAM uses an internal pipelined architecture to achieve high-speed opera-
tion. This architecture is compatible with the 2n rule of prefetch architectures, but it also
allows the column address to be changed on every clock cycle to achieve a high-speed,
fully random access. Precharging one bank while accessing one of the other three banks
will hide the PRECHARGE cycles and provide seamless, high-speed, random-access
operation.
The 64Mb SDRAM is designed to operate in 3.3V, low-power memory systems. An auto
refresh mode is provided, along with a power-saving, power-down mode. All inputs and
outputs are LVTTL-compatible.
SDRAMs offer substantial advances in DRAM operating performance, including the
ability to synchronously burst data at a high data rate with automatic column-address
generation, the ability to interleave between internal banks to hide precharge time and
the capability to randomly change column addresses on each clock cycle during a burst
access.
The automotive temperature (AT) option adheres to the following specifications:
• 16ms refresh rate
• Self refresh not supported
• Ambient and case temperatures cannot be less than –40°C or greater than 105°C
®
64Mb SDRAM is a high-speed CMOS, dynamic random-access memory
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
General Description
©2001 Micron Technology, Inc. All rights reserved.
64Mb: x32 SDRAM