MT48LC2M32B2TG-7:G TR Micron Technology Inc, MT48LC2M32B2TG-7:G TR Datasheet - Page 42
![IC SDRAM 64MBIT 143MHZ 86TSOP](/photos/7/22/72264/557-86-tsop_sml.jpg)
MT48LC2M32B2TG-7:G TR
Manufacturer Part Number
MT48LC2M32B2TG-7:G TR
Description
IC SDRAM 64MBIT 143MHZ 86TSOP
Manufacturer
Micron Technology Inc
Type
SDRAMr
Datasheet
1.MT48LC2M32B2P-6G_TR.pdf
(69 pages)
Specifications of MT48LC2M32B2TG-7:G TR
Format - Memory
RAM
Memory Type
SDRAM
Memory Size
64M (2Mx32)
Speed
143MHz
Interface
Parallel
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
0°C ~ 70°C
Package / Case
86-TSOP
Package
86TSOP-II
Density
64 Mb
Address Bus Width
13 Bit
Operating Supply Voltage
3.3 V
Maximum Clock Rate
143 MHz
Maximum Random Access Time
17|8|5.5 ns
Organization
2Mx32
Address Bus
13b
Access Time (max)
17/8/5.5ns
Operating Supply Voltage (typ)
3.3V
Package Type
TSOP-II
Operating Temp Range
0C to 70C
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
Supply Current
160mA
Pin Count
86
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
557-1076-2
PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5
64MSDRAMx32_2.fm - Rev. J 12/08 EN
10. For a READ without auto precharge interrupted by a READ (with or without auto pre-
11. For a READ without auto precharge interrupted by a WRITE (with or without auto pre-
12. For a WRITE without auto precharge interrupted by a READ (with or without auto pre-
13. For a WRITE without auto precharge interrupted by a WRITE (with or without auto pre-
14. For a READ with auto precharge interrupted by a READ (with or without auto precharge),
15. For a READ with auto precharge interrupted by a WRITE (with or without auto precharge),
16. For a WRITE with auto precharge interrupted by a READ (with or without auto precharge),
17. For a WRITE with auto precharge interrupted by a WRITE (with or without auto precharge),
5. A BURST TERMINATE command cannot be issued to another bank; it applies to the bank
6. All states and sequences not shown are illegal or reserved.
7. READs or WRITEs to bank m listed in the Command (Action) column include READs or
8. Concurrent auto precharge: bank n will initiate the AUTO PRECHARGE command when its
9. Burst in bank n continues as initiated.
represented by the current state only.
WRITEs with auto precharge enabled and READs or WRITEs with auto precharge disabled.
burst has been interrupted by bank m’s burst.
charge), the READ to bank m will interrupt the READ on bank n, CL later (Figure 10 on
page 23).
charge), the WRITE to bank m will interrupt the READ on bank n when registered (Figure 12
on page 25 and Figure 13 on page 26). DQM should be used one clock prior to the WRITE
command to prevent bus contention.
charge), the READ to bank m will interrupt the WRITE on bank n when registered (Figure 20
on page 31), with the data-out appearing CL later. The last valid WRITE to bank n will be
data-in registered one clock prior to the READ to bank m.
charge), the WRITE to bank m will interrupt the WRITE on bank n when registered
(Figure 18 on page 30). The last valid WRITE to bank n will be data-in registered one clock
prior to the READ to bank m.
the READ to bank m will interrupt the READ on bank n, CL later. The precharge to bank n
will begin when the READ to bank m is registered (Figure 27 on page 36).
the WRITE to bank m will interrupt the READ on bank n when registered. DQM should be
used two clocks prior to the WRITE command to prevent bus contention. The precharge to
bank n will begin when the WRITE to bank m is registered (Figure 28 on page 37).
the READ to bank m will interrupt the WRITE on bank n when registered, with the data-out
appearing CL later. The precharge to bank n will begin after
when the READ to bank m is registered. The last valid WRITE to bank n will be data-in regis-
tered one clock prior to the READ to bank m (Figure 29 on page 37).
the WRITE to bank m will interrupt the WRITE on bank n when registered. The precharge to
bank n will begin after
tered. The last valid WRITE to bank n will be data registered one clock prior to the WRITE to
bank m (Figure 30 on page 38).
t
WR is met, where
42
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
WR begins when the WRITE to bank m is regis-
t
WR is met, where
©2001 Micron Technology, Inc. All rights reserved.
64Mb: x32 SDRAM
Commands
t
WR begins