MT48LC2M32B2TG-7:G TR Micron Technology Inc, MT48LC2M32B2TG-7:G TR Datasheet - Page 24
![IC SDRAM 64MBIT 143MHZ 86TSOP](/photos/7/22/72264/557-86-tsop_sml.jpg)
MT48LC2M32B2TG-7:G TR
Manufacturer Part Number
MT48LC2M32B2TG-7:G TR
Description
IC SDRAM 64MBIT 143MHZ 86TSOP
Manufacturer
Micron Technology Inc
Type
SDRAMr
Datasheet
1.MT48LC2M32B2P-6G_TR.pdf
(69 pages)
Specifications of MT48LC2M32B2TG-7:G TR
Format - Memory
RAM
Memory Type
SDRAM
Memory Size
64M (2Mx32)
Speed
143MHz
Interface
Parallel
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
0°C ~ 70°C
Package / Case
86-TSOP
Package
86TSOP-II
Density
64 Mb
Address Bus Width
13 Bit
Operating Supply Voltage
3.3 V
Maximum Clock Rate
143 MHz
Maximum Random Access Time
17|8|5.5 ns
Organization
2Mx32
Address Bus
13b
Access Time (max)
17/8/5.5ns
Operating Supply Voltage (typ)
3.3V
Package Type
TSOP-II
Operating Temp Range
0C to 70C
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
Supply Current
160mA
Pin Count
86
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
557-1076-2
Figure 11:
PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5
64MSDRAMx32_2.fm - Rev. J 12/08 EN
Random READ Accesses
Note:
COMMAND
COMMAND
COMMAND
Data from any READ burst may be truncated with a subsequent WRITE command, and
data from a fixed-length READ burst may be immediately followed by data from a
WRITE command (subject to bus turnaround limitations). The WRITE burst may be
initiated on the clock edge immediately following the last (or last desired) data element
from the READ burst, provided that I/O contention can be avoided. In a given system
ADDRESS
ADDRESS
ADDRESS
Each READ command may be to any bank. DQM is LOW.
CLK
CLK
CLK
DQ
DQ
DQ
T0
BANK,
T0
BANK,
T0
COL n
COL n
BANK,
COL n
READ
READ
READ
CL = 1
CL = 2
T1
T1
T1
BANK,
BANK,
BANK,
READ
COL a
READ
COL a
READ
COL a
D
OUT
n
CL = 3
24
T2
T2
BANK,
BANK,
T2
COL x
COL x
BANK,
READ
READ
READ
COL x
D
D
OUT
OUT
n
a
Micron Technology, Inc., reserves the right to change products or specifications without notice.
T3
T3
T3
BANK,
COL m
BANK,
COL m
READ
READ
READ
BANK,
COL m
D
D
D
OUT
x
OUT
OUT
a
n
T4
T4
T4
NOP
NOP
NOP
D
D
D
OUT
OUT
m
OUT
x
a
T5
T5
NOP
NOP
D
D
OUT
m
OUT
x
©2001 Micron Technology, Inc. All rights reserved.
DON’T CARE
64Mb: x32 SDRAM
T6
NOP
D
OUT
m
Commands