P5010NSE1VNB Freescale Semiconductor, P5010NSE1VNB Datasheet - Page 93

• Manufacturer Part Number: P5010NSE1VNB
• Description: Processors - Application Specialized Tmp Enc 2000/1333
• Manufacturer: Freescale Semiconductor

Specifications of P5010NSE1VNB

• Rohs: yes

This figure shows the AC timing diagram of the local bus interface.
Freescale Semiconductor
For recommended operating conditions, see
Input setup
(for LGTA/LUPWAIT/LFRB)
Input hold
(for LGTA/LUPWAIT/LFRB)
Output delay
(Except LALE)
Output hold
(Except LALE)
Local bus clock to output high impedance
for LAD/LDP
LALE output negation to LAD/LDP output
transition (LATCH hold time)
Note:
1. All signals are measured from BV
2. Skew measured between different LCLKs at BV
3. For purposes of active/float timing measurements, the high impedance or off state is defined to be when the total current
4. t
5. Output hold is negative. This means that output transition happens earlier than the falling edge of LCLK.
delivered through the component pin is less than or equal to the leakage current specification.
determined by LBCR[AHD]. The unit is the eLBC controller clock cycle, which is the internal clock that runs the local bus
controller, not the external LCLK. LCLK cycle = eLBC controller clock cycle
LBCR[AHD] defaults to 0 and eLBC runs at maximum hold time.
LBONOT
is a measurement of the minimum time between the negation of LALE and any change in LAD. t
Parameter
P5020/P5010 QorIQ Integrated Processor Hardware Specifications, Rev. 0
Table 50. Enhanced Local Bus Timing Specifications (continued)
DD
Table
/2 of rising/falling edge of LCLK to BV
3.
Symbol
t
t
t
t
t
t
LBONOT
LBKLOV
LBKLOX
LBKLOZ
LBIVKL
LBIXKL
DD
1
/2.
(LBCR[AHD] = 1)
(LBCR[AHD]=0)
platform clock
platform clock
cycles - 1ns
cycles - 1ns
–3.5
Min
—
—
6
1
2
4
DD
X
Max
/2 of the signal in question.
1.5
—
—
—
—
—
LCRR[CLKDIV]. After power on reset,
2
Electrical Characteristics
Unit
ns
ns
ns
ns
ns
ns
LBONOT
is
Note
—
—
—
5
3
4
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