P5010NSE1VNB Freescale Semiconductor, P5010NSE1VNB Datasheet - Page 146

• Manufacturer Part Number: P5010NSE1VNB
• Description: Processors - Application Specialized Tmp Enc 2000/1333
• Manufacturer: Freescale Semiconductor

Specifications of P5010NSE1VNB

• Rohs: yes

Hardware Design Considerations
dependent and are still under characterization, component values may need adjustment based on the system or environment
noise.
Where:
3.3.3
USB_V
filtering, where USB_V
is system dependent and are still under characterization, component values may need adjustment based on the system or
environment noise.
Where:
3.4
Due to large address and data buses, and high operating frequencies, the device can generate transient power surges and high
frequency noise in its power supply, especially while driving large capacitive loads. This noise must be prevented from reaching
other components in the chip’s system, and the chip itself requires a clean, tightly regulated source of power. Therefore, it is
recommended that the system designer place at least one decoupling capacitor at each V
LV
GV
directly under the device using a standard escape pattern. Others may surround the part.
These capacitors should have a value of 0.01 or 0.1 μF. Only ceramic SMT (surface mount technology) capacitors must be used
to minimize lead inductance, preferably 0402 or 0603 sizes.
In addition, it is recommended that there be several bulk storage capacitors distributed around the PCB, feeding the V
OV
146
DD
DD
DD
, LV
, CV
pin of the chip. These decoupling capacitors should receive their power from separate V
DD
C1 = 2.2 μF ± 10%, X5R, with ESL ≤ 0.5 nH
C2 = 2.2 μF ± 10%, X5R, with ESL ≤ 0.5 nH
F1 = 120 Ω at 100-MHz 2A 25% 0603 Ferrite
F2 = 120 Ω at 100-MHz 2A 25% 0603 Ferrite
Bulk and decoupling capacitors are added, as needed, per power supply design.
C1 = 2.2 μF ± 20%, X5R, with Low ESL (for example, Panasonic ECJ0EB0J225M)
F1 = 120 Ω at 100-MHz 2A 25% Ferrite (for example, Murata BLM18PG121SH1)
Bulk and decoupling capacitors are added, as needed, per power supply design.
_1P0 should be sourced by a filtered V
DD
DD
Decoupling Recommendations
, and GND power planes in the PCB, utilizing short traces to minimize inductance. Capacitors may be placed
, GV
USB_V
XV
DD
DD
, and LV
DD
P5020/P5010 QorIQ Integrated Processor Hardware Specifications, Rev. 0
USB_V
DD
_1P0 is sourced from V
Decoupling
DD
Capacitors
_1P0 Power Supply Filtering
Bulk and
DD
Figure 57. USB_V
planes, to enable quick recharging of the smaller chip capacitors. These bulk capacitors should
_1P0
Figure 56. XV
C1
Decoupling
Capacitors
Bulk and
DD_PL
DD_PL
GND
DD
DD
_1P0 Power Supply Filter Circuit
, is illustrated in
using a star connection. An example solution for USB_V
Power Supply Filter Circuit
C2
C1
GND
Figure
F2
F1
C1
57. The component values in this example filter
F1
DD
1.5 V or 1.8V source
, BV
V
DD
DD
DD_PL
, BV
, OV
Freescale Semiconductor
DD
DD
, OV
, CV
DD
DD
, GV
, CV
DD
DD
_1P0
, BV
DD
DD
,
, and
DD
,