P5010NSE1VNB Freescale Semiconductor, P5010NSE1VNB Datasheet - Page 54

• Manufacturer Part Number: P5010NSE1VNB
• Description: Processors - Application Specialized Tmp Enc 2000/1333
• Manufacturer: Freescale Semiconductor

Specifications of P5010NSE1VNB

• Rohs: yes

Electrical Characteristics
33. See
34. For P5010 mode, the DDR2 controller signals must be left unconnected.
35. Pin must NOT be pulled down during power-on reset.
36. This pin should be connected to GND through a 10kΩ
37. A 1uF to 1.5uF capacitor connected to GND is required on this signal. A list of recommended capacitors are shown in
38. A divider network is required on this signal. See
39. For systems which boot from Local Bus (GPCM)-controlled NOR flash or (FCM)-controlled NAND flash, a pull-up on LGPL4
40. Functionally, this pin is an input, but structurally it is an I/O because it either samples configuration input during reset or
41. If migration from a P4 device, this pin is allowed to be powered by AVDD_CC2. If not migrating, do not connect.
2
This section provides the AC and DC electrical specifications for the chip. The chip is currently targeted to these specifications,
some of which are independent of the I/O cell but are included for a more complete reference. These are not purely I/O buffer
design specifications.
2.1
This section describes the ratings, conditions, and other electrical characteristics.
2.1.1
This table provides the absolute maximum ratings.
Core Group A (core 0) supply voltage
Core Group B (core 1) supply voltage
Platform supply voltage
PLL supply voltage (Core, Platform, DDR)
PLL supply voltage (SerDes, filtered from SV
Fuse Programming Override Supply
DUART, I
management, clocking, debug, I/O voltage select, and JTAG I/O
voltage
eSPI, eSHDC I/O voltage
54
bias generation.
Section 3.6.4.2, “USBn_V
is required.
because it has other manufacturing test functions. This pin is therefore described as an I/O for boundary scan.
Section 2.2, “Power Up Sequencing
2
C, DMA, MPIC, GPIO, system control and power
Electrical Characteristics
Overall DC Electrical Characteristics
Absolute Maximum Ratings
Signal
P5020/P5010 QorIQ Integrated Processor Hardware Specifications, Rev. 0
Parameter
DD
_1P8_DECAP Capacitor
Table 2. Absolute Maximum Operating Conditions
Table 1. Pins Listed by Bus (continued)
and
DD
)
Section 5, “Security Fuse
Section 3.6.4.1, “USB Divider
Options.”
± 0.1%
Signal Description
resistor with a low temperature coefficient of ≤ 25ppm/°C for
AV
V
Symbol
V
V
POV
DD_SRDS
OV
CV
DD_PL
AV
DD_CA
DD_CB
Processor,” for additional details on this signal.
DD
DD
DD
DD
n
Network.”
Pin Number
Package
Maximum Value
1
–0.3 to 1.21
–0.3 to 1.21
–0.3 to 1.65
–0.3 to 3.63
–0.3 to 3.63
–0.3 to 2.75
–0.3 to 1.98
–0.3 to 1.1
–0.3 to 1.1
–0.3 to 1.1
Freescale Semiconductor
Type
Pin
Supply
Power
Unit
V
V
V
V
V
V
V
V
Notes
9, 10,
Note
9,
9,
11
—
—
—
—
1
11
11