P5010NSE1VNB Freescale Semiconductor, P5010NSE1VNB Datasheet - Page 106

• Manufacturer Part Number: P5010NSE1VNB
• Description: Processors - Application Specialized Tmp Enc 2000/1333
• Manufacturer: Freescale Semiconductor

Specifications of P5010NSE1VNB

• Rohs: yes

Electrical Characteristics
Common Mode Voltage, V
To illustrate these definitions using real values, consider the example of a current mode logic (CML) transmitter that has a
common mode voltage of 2.25 V and outputs, TD and TD. If these outputs have a swing from 2.0 V to 2.5 V, the peak-to-peak
voltage swing of each signal (TD or TD) is 500 mV p-p, which is referred to as the single-ended swing for each signal. Because
the differential signaling environment is fully symmetrical in this example, the transmitter output’s differential swing (V
the same amplitude as each signal’s single-ended swing. The differential output signal ranges between 500 mV and –500 mV.
In other words, V
The peak-to-peak differential voltage (V
2.20.2
The SerDes reference clock inputs are applied to an internal PLL whose output creates the clock used by the corresponding
SerDes lanes. The SerDes reference clocks inputs are SD_REF_CLK1 and SD_REF_CLK1 for SerDes bank1, SD_REF_CLK2
and SD_REF_CLK2 for SerDes bank2, and SD_REF_CLK3 and SD_REF_CLK3 for SerDes bank3.
SerDes banks 1–3 may be used for various combinations of the following IP blocks based on the RCW Configuration field
SRDS_PRTCL:
The following sections describe the SerDes reference clock requirements and provide application information.
2.20.2.1
This figure shows a receiver reference diagram of the SerDes reference clocks.
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•
•
SerDes bank 1: PEX1/2/3/4, sRIO1/2, SGMII (1.25 Gbps only) or Aurora.
SerDes bank 2: PEX3, SGMII (1.25 or 3.125 GBaud) or XAUI.
SerDes bank 3: sRIO1, SATA, SGMII (3.125 GBaud) or XAUI.
SerDes Reference Clocks
SerDes Reference Clock Receiver Characteristics
OD
is 500 mV in one phase and –500 mV in the other phase. The peak differential voltage (V
P5020/P5010 QorIQ Integrated Processor Hardware Specifications, Rev. 0
cm
waveform is not referenced to ground. See
and Fall Time,” as an example for differential waveform.
The common mode voltage is equal to half of the sum of the voltages between each conductor of
a balanced interchange circuit and ground. In this example, for SerDes output,
V
complimentary output voltages within a differential pair. In a system, the common mode voltage
may often differ from one component’s output to the other’s input. It may be different between the
receiver input and driver output circuits within the same component. It is also referred to as the DC
offset on some occasions.
cm_out
Figure 37. Receiver of SerDes Reference Clocks
SD_REF_CLKn
SD_REF_CLKn
= (V
DIFFp-p
SD_TXn
) is 1000 mV p-p.
+ V
SD_TXn
) ÷ 2 = (A + B) ÷ 2, which is the arithmetic mean of the two
50 Ω
50 Ω
Figure
Input
Amp
41, “Differential Measurement Points for Rise
Freescale Semiconductor
DIFFp
) is 500 mV.
OD
) has