E909.06A61DC ELMOS Semiconductor, E909.06A61DC Datasheet - Page 25

• Manufacturer Part Number: E909.06A61DC
• Description: Processors - Application Specialized Halios multipurpose sensor IC - Auto
• Manufacturer: ELMOS Semiconductor

Specifications of E909.06A61DC

• Rohs: yes
• Processor Series: EL16
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 8 MHz
• Data Ram Size: 3 kB
• Operating Supply Voltage: 2.25 V to 2.75 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: QFN-32
• Interface Type: I2C, SPI
• Memory Type: Flash, SRAM
• Minimum Operating Temperature: - 40 C
• Number Of Timers: 2

5.4 Addressing Modes
Seven addressing modes for the source operand and four addressing modes for the destination operand can ad-
dress the complete address space with no exceptions. The bit numbers in the table below describe the contents of
the As (source) and Ad (destination) mode bits.
5.5 EL16 Instruction Set
The complete EL16 instruction set consists of 27 instructions. There are three instruction formats:
ÿ
ÿ
ÿ
All dual-operand and single-operand instructions can be byte or word instructions by using .B or .W extensions.
Byte instructions are used to access byte data. Word instructions are used to access word data. If no explicit exten-
sion is used, the instruction is a word instruction.
The source and destination of an instruction are defined by the following fields:
ELMOS Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
As/Ad
00/0
01/1
01/1
01/1
10/-
11/-
11/-
Abbr.
src
dst
As
S-reg
Ad
D-reg
B/W
HALIOS® MULTI PURPOSE SENSOR FOR AUTOMOTIVE
PRODUCTION DATA - NOV 16, 2011
ELMOS Semiconductor AG
Dual-operand
Single-operand
Jump
Addressing Mode
Register mode
Indexed mode
Symbolic mode
Absolute mode
Indirect Register
mode
Indirect auto
increment
Immediate mode
&ADDR
Syntax
@Rn+
ADDR
X(Rn)
@Rn
#N
Rn
Data Sheet
25/71
Description
The source operand defined by As and S-reg
The destination operand defined by Ad and D-reg
The addressing bits responsible for the addressing
mode used for the source (src)
The working register used for the source (src)
The addressing bits responsible for the addressing
mode used for the destination (dst)
The working register used for the destination (dst)
Byte or word operation: 0: word operation, 1: byte
operation
Description
Register contents are operand
(Rn + X) point to the operand. X is stored in the
next word.
(Rn + X) point to the operand. X is stored in the
next word. Indexed mode X(PC) is used.
(Rn + X) point to the operand. X is stored in the
next word. Indexed mode X(0) is used.
Rn is used as a pointer to the
Rn is used as a pointer to the operand. Rn is
incremented afterwards by 1 for .B instructions
and by 2 for .W instructions
The word following the instruction contains the
immediate constant N. Indirect auto-increment
mode @PC+ is used.
QM-No.: 25DS0049E.02
E909.06