DS26514G Maxim Integrated, DS26514G Datasheet - Page 228

• Manufacturer Part Number: DS26514G
• Description: Network Controller & Processor ICs
• Manufacturer: Maxim Integrated

Specifications of DS26514G

• Part # Aliases: 90-26514-G00

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 7: Transmit Elastic Store Full Event (TESF)
Bit 6: Transmit Elastic Store Empty Event (TESEM)
Bit 5: Transmit Elastic Store Slip Occurrence Event (TSLIP)
Bit 4: Transmit SLC96 Multiframe Event (TSLC96) (T1 Mode Only)
Bit 3: Transmit Align Frame Event (TAF) (E1 Mode Only)
Bit 2: Transmit Multiframe Event (TMF)
Bit 1: Loss of Transmit Clock Clear Condition (LOTCC)
Bit 0: Loss of Transmit Clock Condition (LOTC)
19-5856; Rev 4; 5/11
0 = Interrupt masked.
1 = Interrupt enabled.
0 = Interrupt masked.
1 = Interrupt enabled.
0 = Interrupt masked.
1 = Interrupt enabled.
0 = Interrupt masked.
1 = Interrupt enabled.
0 = Interrupt masked.
1 = Interrupt enabled.
0 = Interrupt masked.
1 = Interrupt enabled.
0 = Interrupt masked.
1 = Interrupt enabled.
0 = Interrupt masked.
1 = Interrupt enabled.
TESF
TESF
7
0
TIM1
Transmit Interrupt Mask Register 1
1A0h + (200h x (n - 1)) : where n = 1 to 4
TESEM
TESEM
6
0
TSLIP
TSLIP
5
0
TSLC96
—
4
0
TAF
—
3
0
DS26514 4-Port T1/E1/J1 Transceiver
TMF
TMF
2
0
LOTCC
LOTCC
1
0
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LOTC
LOTC
0
0