DS26514G Maxim Integrated, DS26514G Datasheet - Page 22

• Manufacturer Part Number: DS26514G
• Description: Network Controller & Processor ICs
• Manufacturer: Maxim Integrated

Specifications of DS26514G

• Part # Aliases: 90-26514-G00

19-5856; Rev 4; 5/11
TSSYNCIO
TCHBLK1/
TCHBLK2/
TCHBLK3/
TCHBLK4/
TCHCLK1
TCHCLK2
TCHCLK3
TCHCLK4
NAME
TSIG1
TSIG2
TSIG3
TSIG4
N13
PIN
D5
A6
T4
R6
A5
C7
P7
L7
Output
Output
TYPE
Input/
Input
Note: In default operation, this pin is not used. When GTCR1.528MD is set,
this pin is active. If pin is not used, tie low through a resistor.
Transmit System Synchronization In. This pin is selected when the transmit-
side elastic store is enabled. A pulse at this pin establishes either frame or
multiframe boundaries for the transmit side. Note that if the elastic store is
enabled, frame or multiframe boundary will be established for all transmitters.
Should be tied low in applications that do not use the transmit-side elastic store.
The operation of this signal is synchronous with TSYSCLKn.
Transmit System Synchronization Out. If configured as an output and the
transmit-side elastic store is enabled, an 8kHz pulse synchronous to BPCLK1 will
be generated. This pulse in combination with BPCLK1 can be used as an IBO
master. TSSYNCIO can be used as a source to RSYNCn and TSSYNCIO of
another DS26514 or RSYNC and TSSYNC of other Dallas Semiconductor parts.
Transmit Signaling 1 to 4. When enabled, this input samples signaling bits for
insertion into outgoing PCM data stream. Sampled on the falling edge of TCLKn
when the transmit-side elastic store is disabled. Sampled on the falling edge of
TSYSCLKn when the transmit-side elastic store is enabled. In IBO mode, the
TSIGn streams can run up to 16.384MHz. See
Transmit Channel Block/Transmit Channel Block Clock. A dual function pin.
TCHBLK[1:4]. TCHBLKn is a user-programmable output that can be forced high
or low during any of the channels. It is synchronous with TCLKn when the
transmit-side elastic store is disabled. It is synchronous with TSYSCLKn when
the transmit-side elastic store is enabled. It is useful for blocking clocks to a serial
UART or LAPD controller in applications where not all channels are used such as
Fractional T1, Fractional E1, 384kbps (H0), 768kbps, or ISDN-PRI. Also useful
for locating individual channels in drop-and-insert applications, for external per-
channel loopback, and for per-channel conditioning.
TCHCLK[1:4]. TCHCLKn is a 192kHz (T1) or 256kHz (E1) clock that pulses high
during the LSB of each channel. It can also be programmed to output a gated
transmit bit clock controlled by TCHBLKn. It is synchronous with TCLKn when the
transmit-side elastic store is disabled. It is synchronous with TSYSCLKn when
the transmit-side elastic store is enabled. Useful for parallel-to-serial conversion
of channel data.
FUNCTION
DS26514 4-Port T1/E1/J1 Transceiver
Table 9-9
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