DS26514G Maxim Integrated, DS26514G Datasheet - Page 184
DS26514G
Manufacturer Part Number
DS26514G
Description
Network Controller & Processor ICs
Manufacturer
Maxim Integrated
Datasheet
1.DS26514G.pdf
(305 pages)
Specifications of DS26514G
Part # Aliases
90-26514-G00
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Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Note: See
Bit 7: Loss of Receive Clock Condition Clear (LORCC)
Bit 6: Spare Code Detected Condition Clear (LSPC)
Bit 5: Loop Down Code Detected Condition Clear (LDNC)
Bit 4: Loop Up Code Detected Condition Clear (LUPC)
Bit 3: Loss of Receive Clock Condition Detect (LORCD)
Bit 2: Spare Code Detected Condition Detect (LSPD)
Bit 1 : Loop Down Code Detected Condition Detect (LDND)
Bit 0: Loop Up Code Detected Condition Detect (LUPD)
19-5856; Rev 4; 5/11
0 = Interrupt masked.
1 = Interrupt enabled.
0 = Interrupt masked.
1 = Interrupt enabled.
0 = Interrupt masked.
1 = Interrupt enabled.
0 = Interrupt masked.
1 = Interrupt enabled.
0 = Interrupt masked
1 = Interrupt enabled
0 = Interrupt masked.
1 = Interrupt enabled.
0 = Interrupt masked.
1 = Interrupt enabled.
0 = Interrupt masked.
1 = Interrupt enabled.
RIM3
LORCC
for E1 Mode.
7
0
RIM3 (T1 Mode)
Receive Interrupt Mask Register 3
0A2h + (200h x (n - 1)) : where n = 1 to 4
LSPC
6
0
LDNC
5
0
LUPC
4
0
LORCD
3
0
DS26514 4-Port T1/E1/J1 Transceiver
LSPD
2
0
LDND
1
0
184 of 305
LUPD
0
0
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