GTLP18T612MTDX Fairchild Semiconductor, GTLP18T612MTDX Datasheet - Page 3

• Manufacturer Part Number: GTLP18T612MTDX
• Description: IC UNIV BUS TXRX 18BIT 56TSSOP
• Manufacturer: Fairchild Semiconductor
• Series: 74GTLPr

Specifications of GTLP18T612MTDX

• Logic Type: Universal Bus Transceiver
• Number Of Circuits: 18-Bit
• Current - Output High, Low: 24mA, 24mA
• Voltage - Supply: 3.15 V ~ 3.45 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 56-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Functional Description
taining D-type flip-flop, latch and transparent modes of
operation for the data path. Data flow in each direction is
controlled by the clock enables (CEAB and CEBA), latch
enables (LEAB and LEBA), clock (CLKAB and CLKBA)
and output enables (OEAB and OEBA). The clock enables
(CEAB and CEBA) and the output enables (OEAB and
OEBA) control the 18 bits of data for the A-to-B and B-to-A
directions respectively.
For A-to-B data flow, when CEAB is LOW, the device oper-
ates on the LOW-to-HIGH transition of CLKAB for the flip-
flop and on the HIGH-to-LOW transition of LEAB for the
latch path. That is, if CEAB is LOW and LEAB is LOW the
A data is latched regardless as to the state of CLKAB
(HIGH or LOW) and if LEAB is HIGH the device is in trans-
parent mode. When OEAB is LOW the outputs are active.
When OEAB is HIGH the outputs are HIGH impedance.
The data flow of B-to-A is similar except that CEBA, OEBA,
LEBA, and CLKBA are used.
Logic Diagram
The GTLP18T612 is an 18 bit registered transceiver con-
3
CEAB OEAB LEAB CLKAB A
Truth Table
(Note 3)
Note 3: A-to-B data flow is shown. B-to-A data flow is similar but uses
OEBA, LEBA, CLKBA, and CEBA.
Note 4: Output level before the indicated steady state input conditions were
established, provided that CLKAB was HIGH before LEAB went LOW.
Note 5: Output level before the indicated steady-state input conditions
were established.
X
X
X
H
L
L
L
L
H
L
L
L
L
L
L
L
Inputs
X
H
H
L
L
L
L
L
X
H
X
X
X
L
X
X B
X B
H
H
X B
L
L
0
0
0
Output
(Note 4)
(Note 5)
(Note 5) Clock Inhibit
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B
H
H
Z
L
L
Transparent
of A Data
of A Data
Latched
Clocked
Storage
Storage
Mode