GTLP16612MTDX Fairchild Semiconductor, GTLP16612MTDX Datasheet - Page 2
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GTLP16612MTDX
Manufacturer Part Number
GTLP16612MTDX
Description
IC UNIV BUS TXRX 18BIT 56TSSOP
Manufacturer
Fairchild Semiconductor
Series
74GTLPr
Datasheet
1.GTLP16612MTDX.pdf
(9 pages)
Specifications of GTLP16612MTDX
Logic Type
Universal Bus Transceiver
Number Of Circuits
18-Bit
Current - Output High, Low
32mA, 32mA
Voltage - Supply
3.15 V ~ 3.45 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
56-TSSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
www.fairchildsemi.com
Pin Descriptions
Functional Description
The GTLP16612 combines a universal transceiver function with a TTL to GTLP translation. The A Port and control pins
operate at LVTTL or 5V TTL levels while the B Port operates at GTLP levels. The transceiver logic includes D-type latches
and D-type flip-flops to allow data flow in transparent, latched and clock mode.
The functional operation is described in the truth table below.
Truth Table
(Note 1)
Note 1: A-to-B data flow is shown. B-to-A data flow is similar but uses OEBA, LEBA, CLKBA, and CEBA.
Note 2: Output level before the indicated steady-state input conditions were established, provided that CLKAB was HIGH before LEAB went LOW.
Note 3: Output level before the indicated steady-state input conditions were established.
OEAB
OEBA
CEAB
CEBA
LEAB
LEBA
CLKAB
CLKBA
V
A1–A18
B1–B18
Names
REF
Pin
A-to-B Output Enable (Active LOW)
B-to-A Output Enable (Active LOW)
A-to-B Clock Enable (Active LOW)
B-to-A Clock Enable (Active LOW)
A-to-B Latch Enable (Transparent HIGH)
B-to-A Latch Enable (Transparent HIGH)
A-to-B Clock Pulse
B-to-A Clock Pulse
GTLP Input Reference Voltage
A-to-B TTL Data Inputs or
B-to-A 3-STATE Outputs
B-to-A GTLP Data Inputs or
A-to-B Open Drain Outputs
CEAB
H
X
X
X
L
L
L
L
Description
OEAB
H
L
L
L
L
L
L
L
Inputs
LEAB
X
H
H
L
L
L
L
L
CLKAB
2
Connection Diagram
X
H
X
X
X
L
A
X
X
X
H
H
X
L
L
B
B
B
0
0
0
Output
(Note 2)
(Note 3)
(Note 3)
B
H
H
Z
L
L
Clocked storage
Transparent
Clock inhibit
of A data
of A data
Latched
storage
Mode