C8051F987-GMR Silicon Labs, C8051F987-GMR Datasheet - Page 234
C8051F987-GMR
Manufacturer Part Number
C8051F987-GMR
Description
8-bit Microcontrollers - MCU 8kB 512B RAM
Manufacturer
Silicon Labs
Datasheet
1.C8051F986-GUR.pdf
(322 pages)
Specifications of C8051F987-GMR
Rohs
yes
Core
8051
Processor Series
C8051
Data Bus Width
8 bit
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C8051F99x-C8051F98x
22.1. Supporting Documents
It is assumed the reader is familiar with or has access to the following supporting documents:
22.2. SMBus Configuration
Figure 22.2 shows a typical SMBus configuration. The SMBus specification allows any recessive voltage
between 3.0 V and 5.0 V; different devices on the bus may operate at different voltage levels.
Note: The port pins on C8051F99x-C8051F98x devices are not 5 V tolerant, therefore, the device may only be used
The bi-directional SCL (serial clock) and SDA (serial data) lines must be connected to a positive power
supply voltage through a pullup resistor or similar circuit. Every device connected to the bus must have an
open-drain or open-collector output for both the SCL and SDA lines, so that both are pulled high (recessive
state) when the bus is free. The maximum number of devices on the bus is limited only by the requirement
that the rise and fall times on the bus not exceed 300 ns and 1000 ns, respectively.
234
The I
The I
System Management Bus Specification—Version 1.1, SBS Implementers Forum.
in SMBus networks where the supply voltage does not exceed V
2
2
VDD = 3 V
C-Bus and How to Use It (including specifications), Philips Semiconductor.
C-Bus Specification—Version 2.0, Philips Semiconductor.
Figure 22.2. Typical SMBus Configuration
VDD = 3 V
Master
Device
Rev. 1.1
VDD = 3 V
Device 1
Slave
DD
.
VDD = 3 V
Device 2
Slave
SDA
SCL
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