C8051F987-GMR Silicon Labs, C8051F987-GMR Datasheet - Page 217
C8051F987-GMR
Manufacturer Part Number
C8051F987-GMR
Description
8-bit Microcontrollers - MCU 8kB 512B RAM
Manufacturer
Silicon Labs
Datasheet
1.C8051F986-GUR.pdf
(322 pages)
Specifications of C8051F987-GMR
Rohs
yes
Core
8051
Processor Series
C8051
Data Bus Width
8 bit
- Current page: 217 of 322
- Download datasheet (2Mb)
21.3. Priority Crossbar Decoder
The Priority Crossbar Decoder (Figure 21.3) assigns a priority to each I/O function, starting at the top with
UART0. When a digital resource is selected, the least-significant unassigned Port pin is assigned to that
resource (excluding UART0, which is always at pins 4 and 5). If a Port pin is assigned, the Crossbar skips
that pin when assigning the next selected resource. Additionally, the Crossbar will skip Port pins whose
associated bits in the PnSKIP registers are set. The PnSKIP registers allow software to skip Port pins that
are to be used for analog input, dedicated functions, or GPIO.
Important Note on Crossbar Configuration: If a Port pin is claimed by a peripheral without use of the
Crossbar, its corresponding PnSKIP bit should be set. This applies to the VREF signal, external oscillator
pins (XTAL1, XTAL2), the ADC’s external conversion start signal (CNVSTR), EMIF control signals, and any
selected ADC or Comparator inputs. The PnSKIP registers may also be used to skip pins to be used as
GPIO. The Crossbar skips selected pins as if they were already assigned, and moves to the next unas-
signed pin. Figure 21.3 shows all the possible pins available to each peripheral. Figure 21.4 shows the
Crossbar Decoder priority in an example configuration with no Port pins skipped. Figure 21.5 shows the
same Crossbar example with pins P0.2, P0.3, P1.0, and P1.1 skipped.
SF Signals
PIN I/O
TX0
RX0
SCK
MISO
MOSI
NSS*
SDA
SCL
CP0
CP0A
SYSCLK
CEX0
CEX1
CEX2
ECI
T0
T1
SF Signals
Port pin potentially available to peripheral
Special Function Signals are not assigned by the Crossbar. When
these signals are enabled, the Crossbar must be manually configured
to skip their corresponding port pins.
0
1
2
Figure 21.3. Peripheral Availability on Port I/O Pins
3
P0
4
5
6
7
0
1
Rev. 1.1
2
3
C8051F99x-C8051F98x
P1
4
*NSS is only pinned out in 4-wire SPI mode
5
6
7
0
C8051F98x-C8051F99x devices
P2.0 - P2.6 not available on
1
2
3
P2
4
5
6
7
217
Related parts for C8051F987-GMR
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
Part Number:
Description:
KIT EVALUATION FOR CP2102
Manufacturer:
Silicon Laboratories Inc
Datasheet:
Part Number:
Description:
KIT EVAL FOR CP2103 USB TO UART
Manufacturer:
Silicon Laboratories Inc
Datasheet:
Part Number:
Description:
KIT EVAL FOR CP2201 ETH CTRLR
Manufacturer:
Silicon Laboratories Inc
Datasheet:
Part Number:
Description:
DAUGHTER CARD CAP TOUCH SENSE
Manufacturer:
Silicon Laboratories Inc
Datasheet:
Part Number:
Description:
KIT STARTER CAP TOUCH SENSE
Manufacturer:
Silicon Laboratories Inc
Datasheet:
Part Number:
Description:
DEV KIT FOR C8051F320/F321
Manufacturer:
Silicon Laboratories Inc
Datasheet:
Part Number:
Description:
DEVKIT-F120/21/22/23/24/25/26/27
Manufacturer:
Silicon Laboratories Inc
Datasheet:
Part Number:
Description:
DEV KIT FOR C8051F310/F311
Manufacturer:
Silicon Laboratories Inc
Datasheet:
Part Number:
Description:
DEV KIT F220/221/226/230/231/236
Manufacturer:
Silicon Laboratories Inc
Datasheet:
Part Number:
Description:
DEV KIT F300/301/302/303/304/305
Manufacturer:
Silicon Laboratories Inc
Datasheet:
Part Number:
Description:
DEV KIT FOR C8051F330/F331
Manufacturer:
Silicon Laboratories Inc
Datasheet:
Part Number:
Description:
DEV KIT FOR F005/006/007
Manufacturer:
Silicon Laboratories Inc
Datasheet:
Part Number:
Description:
DEV KIT FOR F020/F021/F022/F023
Manufacturer:
Silicon Laboratories Inc
Datasheet:
Part Number:
Description:
KIT DEV FOR C8051F34X
Manufacturer:
Silicon Laboratories Inc
Datasheet:
Part Number:
Description:
KIT DEV FOR C8051F41X
Manufacturer:
Silicon Laboratories Inc
Datasheet: