C8051F305-GSR Silicon Labs, C8051F305-GSR Datasheet - Page 35
C8051F305-GSR
Manufacturer Part Number
C8051F305-GSR
Description
8-bit Microcontrollers - MCU 2KB 14Pin MCU
Manufacturer
Silicon Labs
Datasheet
1.C8051F301-GSR.pdf
(178 pages)
Specifications of C8051F305-GSR
Rohs
yes
Core
8051
Processor Series
C8051
Data Bus Width
8 bit
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5.
The ADC0 subsystem for the C8051F300/2 consists of two analog multiplexers (referred to collectively as
AMUX0) with 11 total input selections, a differential programmable gain amplifier (PGA), and a 500 ksps, 8-
bit successive-approximation-register ADC with integrated track-and-hold and programmable window
detector (see block diagram in Figure 5.1). The AMUX0, PGA, data conversion modes, and window detec-
tor are all configurable under software control via the Special Function Registers shown in Figure 5.1.
ADC0 operates in both Single-ended and Differential modes, and may be configured to measure any Port
pin, the Temperature Sensor output, or V
enabled only when the AD0EN bit in the ADC0 Control register (ADC0CN) is set to logic 1. The ADC0 sub-
system is in low power shutdown when this bit is logic 0.
Sensor
Temp
ADC0 (8-Bit ADC, C8051F300/2)
GND
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
VDD
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
AMUX0
Figure 5.1. ADC0 Functional Block Diagram
10-to-1
AMUX
AMUX
9-to-1
DD
with respect to any Port pin or GND. The ADC0 subsystem is
X
Rev. 2.9
+
-
AMX0SL
VDD
ADC0CF
C8051F300/1/2/3/4/5
ADC
VDD
8-Bit
SAR
ADC0GT
ADC0LT
ADC0CN
Conversion
Start
16
8
000
001
010
011
1xx
AD0WINT
Comb.
AD0BUSY (W)
Timer 0 Overflow
Timer 2 Overflow
Timer 1 Overflow
CNVSTR Input
Logic
35
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