C8051F305-GSR Silicon Labs, C8051F305-GSR Datasheet - Page 145
C8051F305-GSR
Manufacturer Part Number
C8051F305-GSR
Description
8-bit Microcontrollers - MCU 2KB 14Pin MCU
Manufacturer
Silicon Labs
Datasheet
1.C8051F301-GSR.pdf
(178 pages)
Specifications of C8051F305-GSR
Rohs
yes
Core
8051
Processor Series
C8051
Data Bus Width
8 bit
- Current page: 145 of 178
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15.1.2. Mode 1: 16-bit Counter/Timer
Mode 1 operation is the same as Mode 0, except that the counter/timer registers use all 16 bits. The coun-
ter/timers are enabled and configured in Mode 1 in the same manner as for Mode 0.
15.1.3. Mode 2: 8-bit Counter/Timer with Auto-Reload
Mode 2 configures Timer 0 and Timer 1 to operate as 8-bit counter/timers with automatic reload of the start
value. TL0 holds the count and TH0 holds the reload value. When the counter in TL0 overflows from all
ones to 0x00, the timer overflow flag TF0 (TCON.5) is set and the counter in TL0 is reloaded from TH0. If
Timer 0 interrupts are enabled, an interrupt will occur when the TF0 flag is set. The reload value in TH0 is
not changed. TL0 must be initialized to the desired value before enabling the timer for the first count to be
correct. When in Mode 2, Timer 1 operates identically to Timer 0.
Both counter/timers are enabled and configured in Mode 2 in the same manner as Mode 0. Setting the
TR0 bit (TCON.4) enables the timer when either GATE0 (TMOD.3) is logic 0 or when the input signal /INT0
is active as defined by bit IN0PL in register IT01CF (see
for details on the external input signals /INT0 and /INT1).
/INT0
T0
Crossbar
Pre-scaled Clock
SYSCLK
IN0PL
GATE0
Figure 15.2. T0 Mode 2 Block Diagram
XOR
0
1
TR0
M
T
H
2
CKCON
M
T
2
L
M
T
1
0
1
M
T
0
S
C
A
1
Rev. 2.9
C
S
A
0
G
A
T
E
1
C
T
1
/
M
Section “8.3.2. External Interrupts” on page 73
T
1
1
TMOD
M
T
1
0
TCLK
G
A
T
E
0
C
T
0
/
M
T
0
1
C8051F300/1/2/3/4/5
M
T
0
0
(8 bits)
(8 bits)
TH0
TL0
N
1
P
L
I
N
1
S
L
2
I
IT01CF
N
S
1
L
1
I
N
S
1
L
0
I
N
0
P
L
I
Reload
N
0
S
L
2
I
N
S
0
L
1
I
N
S
0
L
0
I
TR1
TR0
TF1
TF0
IE1
IT1
IE0
IT0
Interrupt
145
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