C8051F305-GSR Silicon Labs, C8051F305-GSR Datasheet - Page 127
C8051F305-GSR
Manufacturer Part Number
C8051F305-GSR
Description
8-bit Microcontrollers - MCU 2KB 14Pin MCU
Manufacturer
Silicon Labs
Datasheet
1.C8051F301-GSR.pdf
(178 pages)
Specifications of C8051F305-GSR
Rohs
yes
Core
8051
Processor Series
C8051
Data Bus Width
8 bit
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13.6. SMBus Status Decoding
The current SMBus status can be easily decoded using the SMB0CN register. In the table below, STATUS
VECTOR refers to the four upper bits of SMB0CN: MASTER, TXMODE, STA, and STO. Note that the
shown response options are only the typical responses; application-specific procedures are allowed as
long as they conform with the SMBus specification. Highlighted responses are allowed but do not conform
to the SMBus specification.
1110
1100
Values Read
0
0
0
0
0
0
X A master START was generated. Load slave address + R/W
0 A master data or address byte
1 A master data or address byte
was transmitted; NACK received.
was transmitted; ACK received.
Table 13.4. SMBus Status Decoding
Current SMbus State
Rev. 2.9
into SMB0DAT.
Set STA to restart transfer.
Abort transfer.
Load next data byte into
SMB0DAT
End transfer with STOP
End transfer with STOP and
start another transfer.
Send repeated START
Switch to Master Receiver
Mode (clear SI without writ-
ing new data to SMB0DAT).
Typical Response Options
C8051F300/1/2/3/4/5
0
1
0
0
0
1
1
0
Written
Values
0
0
1
0
1
1
0
0
X
X
X
X
X
X
X
X
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