C8051F305-GSR Silicon Labs, C8051F305-GSR Datasheet - Page 20
C8051F305-GSR
Manufacturer Part Number
C8051F305-GSR
Description
8-bit Microcontrollers - MCU 2KB 14Pin MCU
Manufacturer
Silicon Labs
Datasheet
1.C8051F301-GSR.pdf
(178 pages)
Specifications of C8051F305-GSR
Rohs
yes
Core
8051
Processor Series
C8051
Data Bus Width
8 bit
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C8051F300/1/2/3/4/5
Perhaps the most unique Port I/O enhancement is the Digital Crossbar. This is essentially a digital switch-
ing network that allows mapping of internal digital system resources to Port I/O pins (See Figure 1.7). On-
chip counter/timers, serial buses, HW interrupts, comparator output, and other digital signals in the control-
ler can be configured to appear on the Port I/O pins specified in the Crossbar Control registers. This allows
the user to select the exact mix of general purpose Port I/O and digital resources needed for the particular
application.
1.5.
The C8051F300/1/2/3/4/5 Family includes an SMBus/I
baud rate configuration. Each of the serial buses is fully implemented in hardware and makes extensive
use of the CIP-51's interrupts, thus requiring very little CPU intervention.
20
Highest
Priority
Lowest
Priority
Serial Ports
SYSCLK
Outputs
SMBus
T0, T1
UART
CP0
PCA
Port Latch
2
2
2
4
2
Figure 1.7. Digital Crossbar Diagram
P0
(P0.0-P0.7)
8
Rev. 2.9
XBR2 Registers
XBR0, XBR1,
Crossbar
Decoder
2
Priority
Digital
C interface and a full-duplex UART with enhanced
8
P0MDIN Registers
P0MDOUT,
Cells
I/O
P0
P0.0
P0.7
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