LPC1788FBD144,551 NXP Semiconductors, LPC1788FBD144,551 Datasheet - Page 85
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LPC1788FBD144,551
Manufacturer Part Number
LPC1788FBD144,551
Description
8-bit Microcontrollers - MCU CORTEX-M3 512KB FL 96KB SRAM 4KB EE USB
Manufacturer
NXP Semiconductors
Datasheet
1.LPC1778FBD144551.pdf
(120 pages)
Specifications of LPC1788FBD144,551
Rohs
yes
Factory Pack Quantity
60
- Current page: 85 of 120
- Download datasheet (2Mb)
NXP Semiconductors
LPC178X_7X
Product data sheet
Table 18.
C
EMCDLYCTL are bypassed. Values guaranteed by design.
[1]
[2]
[3]
Table 19.
C
EMCDLYCTL are bypassed. Values guaranteed by design.
Symbol
t
t
t
t
t
Read cycle parameters
t
t
Write cycle parameters
t
t
Symbol
Common to read and write cycles
T
t
t
t
t
t
t
t
t
t
t
Read cycle parameters
t
t
Write cycle parameters
t
t
h(CAS)
d(WV)
h(W)
d(AV)
h(A)
su(D)
h(D)
d(QV)
h(Q)
d(SV)
h(S)
d(RASV)
h(RAS)
d(CASV)
h(CAS)
d(WV)
h(W)
d(AV)
h(A)
su(D)
h(D)
d(QV)
h(Q)
L
L
cy(clk)
= 10 pF, T
= 10 pF, T
Refers to SDRAM clock signal EMC_CLKx.
The data input set-up time has to be selected with the following margin:
t
The data input hold time has to be selected with the following margin:
t
su(D)
h(D)
+ SDRAM access time board delay time delay time of feedback clock 0.
+ delay time of feedback clock SDRAM access time board delay time 0.
Dynamic characteristics: Dynamic external memory interface, read strategy bits
(RD bits) = 00
Dynamic characteristics: Dynamic external memory interface, read strategy bits
(RD bits) = 01
amb
amb
Parameter
column address strobe hold time
write valid delay time
write hold time
address valid delay time
address hold time
data input set-up time
data input hold time
data output valid delay time
data output hold time
Parameter
clock cycle time
chip select valid delay time
chip select hold time
row address strobe valid delay time
row address strobe hold time
column address strobe valid delay time
column address strobe hold time
write valid delay time
write hold time
address valid delay time
address hold time
data input set-up time
data input hold time
data output valid delay time
data output hold time
=
=
All information provided in this document is subject to legal disclaimers.
40
40
Rev. 4.1 — 15 November 2012
C to 85
C to 85
…continued
C, V
C, V
DD(3V3)
DD(3V3)
= 3.0 V to 3.6 V. All programmable delays
= 3.0 V to 3.6 V. All programmable delays
32-bit ARM Cortex-M3 microcontroller
[2]
[3]
[1]
[2]
[3]
LPC178x/7x
Min
1.3
3.6
1.6
3.4
1.1
5.3
3.7
3.9
0.2
Min
12.5
2.7
1.0
2.7
1.1
2.7
1.2
3.2
1.6
3.3
1.0
5.3
3.7
3.3
0.2
© NXP B.V. 2012. All rights reserved.
Max
3.5
7.7
4.2
7.4
3.0
1.5
5.2
8.7
1.6
Max
-
6.0
3.1
6.0
3.3
6.1
3.3
7.1
4.2
7.3
2.8
1.5
5.2
7.3
1.6
85 of 120
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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