LPC1788FBD144,551 NXP Semiconductors, LPC1788FBD144,551 Datasheet - Page 35

• Manufacturer Part Number: LPC1788FBD144,551
• Description: 8-bit Microcontrollers - MCU CORTEX-M3 512KB FL 96KB SRAM 4KB EE USB
• Manufacturer: NXP Semiconductors

Specifications of LPC1788FBD144,551

• Rohs: yes
• Factory Pack Quantity: 60

NXP Semiconductors
[3]
[4]
[5]
[6]
[7]
[8]
[9]
[10] 5 V tolerant pad (5 V tolerant if V
[11] Open-drain 5 V tolerant digital I/O pad, compatible with I
[12] 5 V tolerant pad (5 V tolerant if V
[13] This pad can be powered from VBAT.
[14] Pad provides special analog functionality.
[15] If the RTC is not used, these pins can be left floating.
[16] When the main oscillator is not used, connect XTAL1 and XTAL2 as follows: XTAL1 can be left floating or can be grounded (grounding
Table 4.
Not all functions are available on all parts. See
LPC178X_7X
Product data sheet
Ball
Row A
1
5
9
13
17
Row B
1
5
9
13
17
Row C
1
5
9
5 V tolerant pad (5 V tolerant if V
levels and hysteresis.
5 V tolerant standard pad (5 V tolerant if V
TTL levels and hysteresis. This pad can be powered by VBAT.
5 V tolerant pad (5 V tolerant if V
providing digital I/O functions with TTL levels and hysteresis and analog input. When configured as a ADC input, digital section of the
pad is disabled.
5 V tolerant fast pad (5 V tolerant if V
levels and hysteresis.
5 V tolerant pad (5 V tolerant if V
providing digital I/O with TTL levels and hysteresis and analog output function. When configured as the DAC output, digital section of the
pad is disabled.
Open-drain 5 V tolerant digital I/O pad, compatible with I
functionality. When power is switched off, this pin connected to the I
configuration applies to all functions on this pin.
Not 5 V tolerant. Pad provides digital I/O and USB functions. It is designed in accordance with the USB specification, revision 2.0
(Full-speed and Low-speed mode only).
functions with TTL levels and hysteresis.
functionality. When power is switched off, this pin connected to the I
configuration applies to all functions on this pin.
function with TTL levels and hysteresis.
is preferred to reduce susceptibility to noise). XTAL2 should be left floating.
Symbol
P3[27]
P1[4]
P1[17]
P3[20]
P1[5]
P3[2]
P1[1]
P4[25]
V
P2[0]
P3[13]
P3[9]
V
DD(3V3)
DD(3V3)
Pin allocation table TFBGA208
Ball Symbol
2
6
10
14
2
6
10
14
2
6
10
DD(3V3)
DD(3V3)
DD(3V3)
DD(3V3)
DD(3V3)
DD(3V3)
V
P1[9]
P1[3]
P1[11]
-
P3[10]
V
P4[29]
P3[19]
-
JTAG_TDI
P3[22]
P3[21]
SS
SS
present; if V
present; if V
present; if V
present; if V
present; if V
DD(3V3)
All information provided in this document is subject to legal disclaimers.
present; if V
Table 2
present; if V
Rev. 4.1 — 15 November 2012
DD(3V3)
DD(3V3)
DD(3V3)
DD(3V3)
DD(3V3)
DD(3V3)
2
2
and
C-bus 400 kHz specification. It requires an external pull-up to provide output
C-bus 1 MHz specification. It requires an external pull-up to provide output
not present, do not exceed 3.6 V) providing digital I/O functions with TTL
not present or configured for an analog function, do not exceed 3.6 V)
not present or configured for an analog function, do not exceed 3.6 V)
not present, do not exceed 3.6 V) with 5 ns glitch filter providing digital I/O
not present, do not exceed 3.6 V) with 20 ns glitch filter providing digital I/O
DD(3V3)
Table 7
not present, do not exceed 3.6 V) providing digital I/O functions with TTL
Ball
3
7
11
15
3
7
11
15
3
7
11
not present, do not exceed 3.6 V) providing digital I/O functions with
2
2
C-bus is floating and does not disturb the I
C-bus is floating and does not disturb the I
(EMC pins).
Symbol
P1[0]
P1[14]
P4[15]
P0[8]
-
P3[1]
P4[30]
P1[6]
P4[14]
-
P5[4]
P1[8]
P4[28]
32-bit ARM Cortex-M3 microcontroller
Ball
4
8
12
16
4
8
12
16
4
8
12
LPC178x/7x
Symbol
P4[31]
P1[15]
V
P1[12]
-
P3[0]
P4[24]
P0[4]
P4[13]
-
P0[2]
P1[10]
P0[5]
SS
2
2
© NXP B.V. 2012. All rights reserved.
C lines. Open-drain
C lines. Open-drain
35 of 120