AT45DB161E-SSHD-B Adesto Technologies, AT45DB161E-SSHD-B Datasheet - Page 44
![no-image](/images/no-image-200.jpg)
AT45DB161E-SSHD-B
Manufacturer Part Number
AT45DB161E-SSHD-B
Description
Flash 16M 2.5-3.6V 85Mhz Serial Flash
Manufacturer
Adesto Technologies
Datasheet
1.AT45DB161E-SHD-B.pdf
(72 pages)
Specifications of AT45DB161E-SSHD-B
Rohs
yes
Data Bus Width
8 bit
Memory Type
Data Flash
Memory Size
16 Mbit
Architecture
Flexible, Uniform Erase
Timing Type
Synchronous
Interface Type
SPI
Supply Voltage - Max
3.6 V
Supply Voltage - Min
2.5 V
Maximum Operating Current
26 mA
Operating Temperature
- 40 C to + 85 C
Mounting Style
SMD/SMT
Package / Case
SOIC-8
Factory Pack Quantity
100
16.
16.1
Power-On/Reset State
When power is first applied to the device, or when recovering from a reset condition, the device will default to SPI
Mode 3. In addition, the output pin (SO) will be in a high impedance state, and a high-to-low transition on the CS pin will
be required to start a valid instruction. The SPI mode (Mode 3 or Mode 0) will be automatically selected on every falling
edge of CS by sampling the inactive clock state.
Initial Power-Up Timing Restrictions
During power-up, the device must not be accessed for at least the minimum t
the minimum V
device in a reset mode until the supply voltage rises above the maximum POR threshold value (V
all operations are disabled and the device will not respond to any commands. After power-up, the device will be in the
standby mode.
If the first operation to the device after power-up will be a program or erase operation, then the operation cannot be
started until the supply voltage reaches the minimum V
be a maximum time of t
Table 16-1. Power-Up Timing
Figure 16-1. Power-Up Timing
Symbol
t
t
V
V
VCSL
PUW
V
POR
POR
V
POR
CC
(max)
V
(min)
(min)
CC
Parameter
Minimum V
Power-Up Device Delay Before Program or Erase Allowed
Power-On Reset (POR) Voltage
CC
level. While the device is being powered-up, the internal Power-On Reset (POR) circuitry keeps the
During this Time
Do Not Attempt
Device Access
PUW
CC
to Chip Select Low Time
.
CC
t
VCSL
t
PUW
level and an internal device delay has elapsed. This delay will
Adesto AT45DB161E [DATASHEET]
Read Operation Permitted
VCSL
Program/Erase Operations Permitted
time after the supply voltage reaches
Min
1.5
70
8782D–DFLASH–11/2012
POR
). During this time,
Max
2.2
5
Time
Units
ms
μs
V
44