iCE65L01F-LCB81C Lattice, iCE65L01F-LCB81C Datasheet - Page 38

• Manufacturer Part Number: iCE65L01F-LCB81C
• Description: FPGA - Field Programmable Gate Array iCE65 1280 LUTs, 1.0 1.2V Ultra Low-Power
• Manufacturer: Lattice

Specifications of iCE65L01F-LCB81C

• Rohs: yes
• Number Of Gates: 1280
• Number Of Logic Blocks: 16
• Number Of I/os: 63
• Maximum Operating Frequency: 256 MHz
• Operating Supply Voltage: 1.2 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: CBGA-81
• Distributed Ram: 64 Kbit
• Minimum Operating Temperature: 0 C
• Operating Supply Current: 12 uA
• Factory Pack Quantity: 490

iCE65 Ultra Low-Power mobileFPGA
JTAG Boundary Scan Port
(2.42, 30-MAR-2012)
38
Overview
Each iCE65 device includes an IEEE 1149.1-compatible JTAG boundary-scan port. The port supports printed-circuit
board (PCB) testing and debugging. It also provides an alternate means to configure the iCE65 device.
Signal Connections
Table 31
the Application Processor’s (AP) I/O supply rail and the iCE65’s SPI and VCCIO_2 bank supply rails all connect to
the same voltage. The second scenario is when the AP’s I/O supply voltage is greater than the iCE65’s VCCIO_2
supply voltage.
The JTAG port connections are listed in
* Must be tied off to GND or VCCIO_1, else VCCIO_1 draws current.
Table 33
package types. The JTAG port is located in I/O Bank 1 along the right edge of the iCE65 device and powered by the
VCCIO_1 supply inputs. Consequently, the JTAG interface uses the associated I/O standards for I/O Bank 1.
= VCC_SPI
= VCCIO_2
> VCCIO_2
TDI
TMS
TCK
TDO
TRST_B
VCCIO_AP
VCCIO_AP
AP_VCCIO
Condition
Signal
Name
JTAG Interface
describes how to maintain voltage compatibility for two interface scenarios. The easiest interface is when
lists the ball/pin numbers for the JTAG interface by package code. The JTAG interface is available in select
TRST_B
TMS
TDO
TCK
TDI
Direction
Direct
Output
Input
Input
Input
Input
N/A
OK
Table 33:
Table 31:
Required,
requires
OK with
Open-
CRESET_B
pull-up
pull-up
Drain
Table 32:
Test Data Input. Must be tied off to GND when unused. (no pull-up resistor)*
Test Mode Select. Must be tied off to GND when unused. (no pull-up resistor)*
Test Clock. Must be tied off to GND when unused. (no pull-up resistor)*
Test Data Output.
Test Reset, active Low. Must be Low during normal device operation. Must be High
to enable JTAG operations.*
VQ100
JTAG Interface Ball/Pin Numbers by Package
N/A
CRESET_B and CDONE Voltage Compatibility
Table
Required if
open-drain
Pull-up
Required
iCE65 JTAG Boundary Scan Signals
output
using
32.
™
CB132
Family
Recommended
CDONE Pull-
M12
M14
P14
N14
L12
Required
up
Description
AP can directly drive CRESET_B High and
Low although an open-drain output
recommended is if multiple devices control
CRESET_B. If using an open-drain driver,
the CRESET_B input must include a 10 kΩ
pull-up resistor to VCCIO_2. The 10 kΩ
pull-up resistor to AP_VCCIO is also
recommended.
The AP must control CRESET_B with an
open-drain output, which requires a 10 kΩ
pull-up resistor to VCCIO_2. The 10 kΩ
pull-up resistor to AP_VCCIO is required.
CB196
M12
N14
M14
P14
L12
Lattice Semiconductor Corporation
Requirement
CB284
U18
T16
V18
R16
T18
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