iCE65L01F-LCB81C Lattice, iCE65L01F-LCB81C Datasheet - Page 20

• Manufacturer Part Number: iCE65L01F-LCB81C
• Description: FPGA - Field Programmable Gate Array iCE65 1280 LUTs, 1.0 1.2V Ultra Low-Power
• Manufacturer: Lattice

Specifications of iCE65L01F-LCB81C

• Rohs: yes
• Number Of Gates: 1280
• Number Of Logic Blocks: 16
• Number Of I/os: 63
• Maximum Operating Frequency: 256 MHz
• Operating Supply Voltage: 1.2 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: CBGA-81
• Distributed Ram: 64 Kbit
• Minimum Operating Temperature: 0 C
• Operating Supply Current: 12 uA
• Factory Pack Quantity: 490

iCE65 Ultra Low-Power mobileFPGA
(2.42, 30-MAR-2012)
20
Differential Global Buffer Input
All eight global buffer inputs support single-ended I/O standards such as LVCMOS. Global buffer GBUF7 in I/O
Bank 3 also provides an optional direct SubLVDS, LVDS, or LVPECL differential clock input, as shown in
The GBIN7 and its associated differential I/O pad accept a differential clock signal. A 100 Ω termination resistor is
required across the two pads. Optionally, swap the outputs from the LVDS or LVPECL clock driver to invert the
clock as it enters the iCE65 device.
Table 15
differential input is the only one that connects directly to a global buffer, other differential inputs can connect to a
global buffer using general-purpose interconnect, with slightly more signal delay.
Differential Global
GBIN7/DPxxB
Buffer Input
!
!
(GBIN)
DPxxA
lists the pin or ball numbers for the differential global buffer input by package style. Although this
Note the clock differences between the iCE65L04 and iCE65L08 in the CB196 package.
The differential global buffer input is not available for iCE65 devices in the CB132 package. This
restriction is an artifact of the pin compatibility between the CB132 and CB284 package.
Note the clock differences between the iCE65L04 and iCE65L08 in the CB196 package.
Table 15:
Bank
I/O
3
Differential Global Buffer Input Ball/Pin Number by Package
GBUF
Figure 16: LVDS or LVPECL Clock Input
VQ100
LVPECL
LVDS/
Driver
Clock
13
12
Figure 15: GBIN/PIO Pin
OUT
IN
OE
™
iCEGATE
Optional connection from internal
programmable interconnect.
GBIN/PIO Pin
CB132
Family
Disabled
HOLD
Enabled
N/A
N/A
GBIN7/DP##B
‘1’
‘0’
DP##A
HD
Latch inhibits
switching for
lowest power
0 = Hi-Z
1 = Output
GBUF7
CB196
‘L04
GBIN pins optionally
connect directly to an
associated GBUF global
buffer
G1
G2
Enabled
Lattice Semiconductor Corporation
VCCIO
Pull-up
Enable
Pull-up
not in I/O
Bank 3
CB196
PAD
‘L08
H3
H4
www.latticesemi.com
CB284
Figure
L5
L3
16.