iCE65L01F-LCB81C Lattice, iCE65L01F-LCB81C Datasheet - Page 31

• Manufacturer Part Number: iCE65L01F-LCB81C
• Description: FPGA - Field Programmable Gate Array iCE65 1280 LUTs, 1.0 1.2V Ultra Low-Power
• Manufacturer: Lattice

Specifications of iCE65L01F-LCB81C

• Rohs: yes
• Number Of Gates: 1280
• Number Of Logic Blocks: 16
• Number Of I/os: 63
• Maximum Operating Frequency: 256 MHz
• Operating Supply Voltage: 1.2 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: CBGA-81
• Distributed Ram: 64 Kbit
• Minimum Operating Temperature: 0 C
• Operating Supply Current: 12 uA
• Factory Pack Quantity: 490

Lattice Semiconductor Corporation
www.latticesemi.com
The Lattice iCEman65 development board and associated programming software uses an ST Micro/Numonyx
M25Pxx SPI serial Flash PROM.
SPI PROM Size Requirements
Table 27
but not required unless the end application uses the additional space. SPI serial PROM sizes are specified in bits.
For each device size, the table shows the required minimum PROM size for “Logic Only” (no BRAM initialization)
and “Logic + RAM4K” (RAM4K blocks pre-initialized). Furthermore, the table shows the PROM size for varying
numbers of configuration images. Most applications will use a single image. Applications that use the Cold Boot or
Warm Boot features may use more than one image.
Enabling SPI Configuration Interface
To enable the SPI configuration mode, the SPI_SS_B pin must be allowed to float High. The SPI_SS_B pin has an
internal pull-up resistor. If SPI_SS_B is Low, then the iCE65 component defaults to the SPI Slave configuration
mode.
SPI Master Configuration Process
The iCE65 SPI Master Configuration Interface supports a variety of modern, high-density, low-cost SPI serial Flash
PROMs. Most modern SPI PROMs include a power-saving Deep Power-down mode. The iCE65 component
exploits this mode for additional system power savings.
The iCE65 SPI interface starts by driving
the SPI PROM, hexadecimal command code 0xAB.
wakes up the SPI PROM if it is already in Deep Power-down mode. If the PROM is not in Deep Power-down mode,
the extra command has no adverse affect other than that it requires a few additional microseconds during the
configuration process. The iCE65 device transmits data on the
output. The SPI PROM does not provide any data to the iCE65 device’s
command bit, the iCE65 device de-asserts SPI_SS_B High, completing the command. The iCE65 device then waits a
minimum of 10 µS before sending the next SPI PROM command.
iCE65L01
iCE65L04
iCE65L08
Device


For lowest possible power consumption after configuration, the PROM should also support the 0xB9 Deep
Power Down command and the 0xAB Release from Deep Power-down Command (see
26). The low-power mode is optional.
The PROM must be ready to accept commands 10 µs after meeting its power-on conditions. In the PROM
data sheet, this may be specified as t
CRESET_B input Low until the PROM is ready, then releasing CRESET_B, either under program control or
using an external power-on reset circuit.
lists the minimum SPI PROM size required to configure an iCE65 device. Larger PROM sizes are allowed,
Table 27:
Logic
Only
256K
512K
1M
1 Image
Smallest SPI PROM Size (bits), by Device, by Number of Images
Logic +
RAM4K
256K
1M
2M
SPI_SS_B
Logic
Only
512K
1M
2M
VSL
2 Images
or t
Figure 24
Low, and then sends a Release from Power-down command to
Logic +
RAM4K
VCSL
512K
2M
4M
. It is possible to use slower PROMs by holding the
provides an example waveform. This initial command
SPI_SO
Logic
Only
1M
2M
4M
output, on the falling edge of the
3 Images
SPI_SI
Logic +
RAM4K
1M
2M
4M
input. After sending the last
(2.42, 30-MAR-2011)
Figure 24
Logic
Only
1M
2M
4M
4 Images
and
Logic +
RAM4K
SPI_SCK
Figure
1M
4M
8M
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