iCE65L01F-LCB81C Lattice, iCE65L01F-LCB81C Datasheet - Page 16

• Manufacturer Part Number: iCE65L01F-LCB81C
• Description: FPGA - Field Programmable Gate Array iCE65 1280 LUTs, 1.0 1.2V Ultra Low-Power
• Manufacturer: Lattice

Specifications of iCE65L01F-LCB81C

• Rohs: yes
• Number Of Gates: 1280
• Number Of Logic Blocks: 16
• Number Of I/os: 63
• Maximum Operating Frequency: 256 MHz
• Operating Supply Voltage: 1.2 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: CBGA-81
• Distributed Ram: 64 Kbit
• Minimum Operating Temperature: 0 C
• Operating Supply Current: 12 uA
• Factory Pack Quantity: 490

iCE65 Ultra Low-Power mobileFPGA
(2.42, 30-MAR-2012)
16
Input and Output Register Control per PIO Pair
Figure 11:
PIO pins are grouped into pairs for synchronous control. Registers within pairs of PIO pins share common input
clock, output clock, and I/O clock enable control signals, as illustrated in
are removed from the drawing for clarity.
The INCLK clock signal only controls the input flip-flops within the PIO pair.
The OUTCLK clock signal controls the output flip-flops and the output-enable flip-flops within the PIO pair.
If desired in the iCE65 application, the INCLK and OUTCLK signals can be connected together.
The IOENA clock-enable input, if used, enables all registers in the PIO pair, as shown in
registers are always enabled.
The pairing of PIO pairs is most evident in the tables in
!
PIO Pairs Share Clock and Clock Enable Controls (only registered paths shown for clarity)
Before laying out your printed-circuit board, run the design through the iCEcube development software to
verify that your selected pinout complies with these I/O register pairing requirements. See
Cross
Reference” starting on page 84.
OUTCLK
IOENA
INCLK
OUT
OUT
OE
OE
IN
IN
= Statically defined by configuration program
EN
EN
1
™
Family
“Die Cross
EN
EN
EN
EN
Reference” starting on page 84.
Figure
Lattice Semiconductor Corporation
0 = Hi-Z
1 = Output Enabled
0 = Hi-Z
1 = Output Enabled
11. The combinational logic paths
PIO Pair
PAD
PAD
Figure
www.latticesemi.com
tables in
11. By default, the
“Die