iCE65L01F-LCB81C Lattice, iCE65L01F-LCB81C Datasheet - Page 36

• Manufacturer Part Number: iCE65L01F-LCB81C
• Description: FPGA - Field Programmable Gate Array iCE65 1280 LUTs, 1.0 1.2V Ultra Low-Power
• Manufacturer: Lattice

Specifications of iCE65L01F-LCB81C

• Rohs: yes
• Number Of Gates: 1280
• Number Of Logic Blocks: 16
• Number Of I/os: 63
• Maximum Operating Frequency: 256 MHz
• Operating Supply Voltage: 1.2 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: CBGA-81
• Distributed Ram: 64 Kbit
• Minimum Operating Temperature: 0 C
• Operating Supply Current: 12 uA
• Factory Pack Quantity: 490

iCE65 Ultra Low-Power mobileFPGA
(2.42, 30-MAR-2012)
36
CRESET_B
SPI_SS_B
SPI_SCK
SPI_SO
CDONE
SPI_SI
After driving CRESET_B High or allowing it to float High, the AP must wait a minimum of t
allowing the iCE65 FPGA to clear its internal configuration memory.
After waiting for the configuration memory to clear, the AP sends the configuration image generated by the iCEcube
development system. An SPI peripheral mode configuration image must not use the ColdBoot or WarmBoot
options. Send the entire configuration image, without interruption, serially to the iCE65’s SPI_SI input on the falling
edge of the SPI_SCK clock input. Once the AP sends the 0x7EAA997E synchronization pattern, the generated
SPI_SCK clock frequency must be within the specified 1 MHz to 25 MHz range (40 ns to 1 µs clock period) while
sending the configuration image. Send each byte of the configuration image with most-significant bit (msb) first.
The AP sends data to the iCE65 FPGA on the falling edge of the SPI_SCK clock. The iCE65 FPGA internally
captures each incoming SPI_SI data bit on the rising edge of the SPI_SCK clock. The iCE65’s SPI_SO output pin is
not used during SPI peripheral mode but must connect to the AP if the AP also programs the iCE65’s Nonvolatile
Configuration Memory (NVCM).
After sending the entire image, the iCE65 FPGA releases the CDONE output allowing it to float High via the 10 kΩ
pull-up resistor to AP_VCC. If the CDONE pin remains Low, then an error occurred during configuration and the
AP should handle the error accordingly for the application.
After the CDONE output pin goes High, send at least 49 additional dummy bits, effectively 49 additional SPI_SCK
clock cycles measured from rising-edge to rising-edge.
After the additional SPI_CLK cycles, the SPI interface pins then become available to the user application loaded in
FPGA.
To reconfigure the iCE65 FPGA or to load a different configuration image, merely restart the configuration process
by pulsing CRESET_B Low or power-cycling the FPGA.
Figure 29:
!
!
Pulled High in SPI_SO pin via internal pull-up resistor. Not used for SPI Peripheral mode configuration. Used when programming NVCM via SPI itnterface.
≥ 200 ns
Prior to sending the iCE65 configuration image , an SPI NVCM shut-off sequence must be sent.
The iCE65 configuration image must be sent as one contiguous stream without interruption.
The SPI_SCK clock period must be between 40 ns to 1 µs (1 MHz to 25 MHz).
The iCE65 configuration image must be sent as one contiguous stream without interruption.
The SPI_SCK clock period must be between 40 ns to 1 µs (1 MHz to 25 MHz).
See AN014 for details.
Application Processor Waveforms for SPI Peripheral Mode Configuration Process
iCE65 enters SPI Peripheral
mode with SPI_SS_B = Low on
rising edge of CRESET_B
iCE65L08: ≥ 1200 µs
iCE65L01: ≥ 800 µs
iCE65L04: ≥ 800 µs
configuration memory
iCE65 clears internal
Configuration image always starts with 0x7EAA997E synchronization word.
iCE65 captures SPI_SI data on SPI_SCK rising edge.
™
Send most-significant bit of each byte first
Family
Entire Configuration Images
Lattice Semiconductor Corporation
X X X
49 SPI_SCK Cycles
Rising edge to rising edge
CR_SCK
49 dummy bits
Don’t Care
www.latticesemi.com
µs, (see
X X X
Table
60)