iCE65L01F-LCB81C Lattice, iCE65L01F-LCB81C Datasheet - Page 19

• Manufacturer Part Number: iCE65L01F-LCB81C
• Description: FPGA - Field Programmable Gate Array iCE65 1280 LUTs, 1.0 1.2V Ultra Low-Power
• Manufacturer: Lattice

Specifications of iCE65L01F-LCB81C

• Rohs: yes
• Number Of Gates: 1280
• Number Of Logic Blocks: 16
• Number Of I/os: 63
• Maximum Operating Frequency: 256 MHz
• Operating Supply Voltage: 1.2 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: CBGA-81
• Distributed Ram: 64 Kbit
• Minimum Operating Temperature: 0 C
• Operating Supply Current: 12 uA
• Factory Pack Quantity: 490

Lattice Semiconductor Corporation
www.latticesemi.com
Table 12:
Table 12
(PIO) pair. Although there is no direct connection between a global buffer and a PIO output, such a connection is
possible by first connecting through a PLB LUT4 function. Again, all global buffers optionally drive all clock inputs.
However, even-numbered global buffers optionally drive the clock-enable input on a PIO pair.
Global Buffer Inputs
The iCE65 component has eight specialized GBIN/PIO pins that are optionally direct inputs to the global buffers,
offering the best overall clock characteristics. As shown in
but also provides a direct connection to its associated global buffer. The direct connection to the global buffer
bypasses the iCEgate input-blocking latch and other PIO input logic. These special PIO pins are allocated two to an
I/O Bank, a total of eight. These pins are labeled GBIN0 through GBIN7, as shown in
for each GBIN input appear in
Global Buffer
Input (GBIN)
Global Buffer
Global Buffer
!
Table 13:
GBIN0
GBIN1
GBIN2
GBIN3
GBIN4
GBIN5
GBIN6
GBIN7
GBUF0
GBUF1
GBUF2
GBUF3
GBUF4
GBUF5
GBUF6
GBUF7
GBUF0
GBUF1
GBUF2
GBUF3
GBUF4
GBUF5
GBUF6
GBUF7
and
iCE65L01 & iCE65L04: Global Buffer (GBUF) Connections to Programmable I/O (PIO) Pair
The PIO clock enable connect is different between the iCE65L01/iCE65L04 and iCE65L08.
Table 13
iCE64L08: Global Buffer (GBUF) Connections to Programmable I/O (PIO) Pair
Table 14:
list the connections between a specific global buffer and the inputs on a Programmable I/O
Bank
I/O
No (connect through
No (connect through
0
1
2
3
Connections
Connections
Table
PLB LUT)
PLB LUT)
Output
Output
Global Buffer Input Ball/Pin Number by Package
VQ100
14.
90
89
63
62
34
33
15
13
CB132
G14
F14
Input Clock
Input Clock
H1
G1
A6
A7
P8
P7
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Figure
CB196
‘L04
15, each GBIN/PIO pin is a full-featured I/O pin
G12
F10
H1
G1
A7
E7
P5
L7
Output Clock
Output Clock
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
CB196
‘L08
G12
F10
M7
N8
H1
H3
A7
E7
Figure 14
(2.42, 30-MAR-2011)
and the pin locations
CB284
Clock Enable
Clock Enable
E10
E11
K18
V12
V11
L18
M5
L5
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
No
No
No
No
No
No
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