M24LR16E-RDW6T/2 STMicroelectronics, M24LR16E-RDW6T/2 Datasheet - Page 40

• Manufacturer Part Number: M24LR16E-RDW6T/2
• Description: EEPROM 16kB EEPROM Dual INT 400 kHz IC2 13.56MHz
• Manufacturer: STMicroelectronics

Specifications of M24LR16E-RDW6T/2

• Product Category: EEPROM
• Rohs: yes
• Memory Size: 16 Kbit
• Organization: 256 x 8
• Data Retention: 40 yr
• Maximum Clock Frequency: 400 KHz
• Maximum Operating Current: 50 mA
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: TSSOP-8
• Access Time: 900 ns
• Interface Type: 2-Wire Serial, I2C
• Minimum Operating Temperature: -40 C
• Operating Current: 50 mA

I
5.16
5.16.1
Figure 12. I
40/143
2
C device operation
Device select code = 1010 1 1 1
Ack generated during 9
Device select
Validation
code 09h
code
M24LR16E-R I
The M24LR16E-R controls I
the 64-bit I2C_Write_Lock bit area. The I
commands: I C present password and I
I
The I
M24LR16E-R in order to modify the write access rights of all the memory sectors protected
by the I2C_Write_Lock bits, including the password itself. If the presented password is
correct, the access rights remain activated until the M24LR16E-R is powered off or until a
new I
Following a Start condition, the bus master sends a device select code with the Read/Write
bit (RW) reset to 0 and the Chip Enable bit E2 at 1. The device acknowledges this, as shown
in
responds to each address byte with an acknowledge bit, and then waits for the four
password data bytes, the validation code, 09h, and a resend of the four password data
bytes. The most significant byte of the password is sent first, followed by the least significant
bytes.
It is necessary to send the 32-bit password twice to prevent any data corruption during the
sequence. If the two 32-bit passwords sent are not exactly the same, the M24LR16E-R does
not start the internal comparison.
When the bus master generates a Stop condition immediately after the Ack bit (during the
tenth bit time slot), an internal delay equivalent to the write cycle time is triggered. A Stop
condition at any other time does not trigger the internal delay. During that delay, the
M24LR16E-R compares the 32 received data bits with the 32 bits of the stored I
password. If the values match, the write access rights to all protected sectors are modified
after the internal delay. If the values do not match, the protected sectors remains protected.
During the internal delay, the serial data (SDA) signal is disabled internally, and the device
does not respond to any requests.
2
2
C present password command
C present password command description
Figure
R/W
Ack
2
Ack
2
C present password command is used in I
C present password command is issued.
Password
address 09h
[31:24]
12, and waits for two I
Password
th
bit time slot.
Ack
Ack
Password
2
address 00h
[23:16]
Password
C password security
2
C sector write access using the 32-bit-long I
Ack
Doc ID 018932 Rev 8
Ack
2
C password address bytes 09h and 00h. The device
Password
Password
[15:8]
[31:24]
2
C write password.
2
C password value is managed using two I
Ack
Ack
Password
2
Password
[7:0]
C mode to present the password to the
[23:16]
Ack
Ack
Password
[15:8]
Ack
2
C password and
Password
[7:0]
M24LR16E-R
2
C
ai15125c
Ack
2
C