M24LR16E-RDW6T/2 STMicroelectronics, M24LR16E-RDW6T/2 Datasheet

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... More than 1 million write cycles More than 40-year data retention Multiple password protection in RF mode Single password protection in I Package – ECOPACK2 Halogen-free) Doc ID 018932 Rev 8 M24LR16E-R Datasheet production data SO8 (MN) 150 mils width UFDFPN8 (MC TSSOP8 (DW mode ...

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... Antenna coil (AC0, AC1 2.5.1 2.6 V ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 SS 2.7 Supply voltage (V 2.7.1 2.7.2 2.7.3 2.7.4 3 User memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4 System memory area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.1 M24LR16E-R block security in RF mode . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.1.1 4.2 M24LR16E-R block security in I²C mode (I2C_Write_Lock bit area 4.3 Configuration byte and Control register . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4.3.1 4.3.2 4.3.3 4.3.4 4.3.5 4.4 ISO 15693 system parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . device operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5 ...

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... Communication signal from VCD to M24LR16E Data rate and data coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 9.1 Data coding mode: 1 out of 256 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 9.2 Data coding mode: 1 out 9.3 VCD to M24LR16E-R frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 I²C timeout on Start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 I²C timeout on clock period . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . password security . . . . . . . . . . . . . . . . . . . . . . . . . . . . present password command description . . . . . . . . . . . . . . . . . . . . . 40 ...

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... Subcarrier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 10.3 Data rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 11 Bit representation and coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 11.1 Bit coding using one subcarrier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 11.1.1 11.1.2 11.2 Bit coding using two subcarriers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 11.2.1 11.2.2 12 M24LR16E-R to VCD frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 12.1 SOF when using one subcarrier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 12.1.1 12.1.2 12.2 SOF when using two subcarriers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 12.2.1 12.2.2 12.3 EOF when using one subcarrier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 12.3.1 12.3.2 12.4 EOF when using two subcarriers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 12 ...

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... Explanation of the possible cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 24 Inventory Initiated command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 25 Timing definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 25.1 t1: M24LR16E-R response delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 25.2 t2: VCD new request delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 25 VCD new request delay when no response is received 3 from the M24LR16E Command codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 26.1 Inventory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 26.2 Stay Quiet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Doc ID 018932 Rev 8 Contents 5/143 ...

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... Fast Read Multiple Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 26.21 Inventory Initiated . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 26.22 Initiate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 26.23 ReadCfg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 26.24 WriteEHCfg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 26.25 WriteDOCfg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 26.26 SetRstEHEn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 26.27 CheckEHEn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 27 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 29 RF electrical parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 30 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 31 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 6/143 Doc ID 018932 Rev 8 M24LR16E-R ...

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... M24LR16E-R Appendix A Anticollision algorithm (informative 138 A.1 Algorithm for pulsed slots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 Appendix B CRC (informative 139 B.1 CRC error detection method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 B.2 CRC calculation example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 Appendix C Application family identifier (AFI) (informative 141 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 Doc ID 018932 Rev 8 Contents 7/143 ...

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... Response data rates Table 21. UID format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Table 22. CRC transmission rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Table 23. VCD request frame format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Table 24. M24LR16E-R Response frame format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Table 25. M24LR16E-R response depending on Request_flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Table 26. General request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Table 27. Definition of request flags Table 28. Request flags when Bit Table 29 ...

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... M24LR16E-R Table 49. Sector security status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Table 50. Read Multiple Block response format when Error_flag is set . . . . . . . . . . . . . . . . . . . . . . . 90 Table 51. Select request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Table 52. Select Block response format when Error_flag is NOT set Table 53. Select response format when Error_flag is set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Table 54. Reset to Ready request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Table 55. ...

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... Table 129. TSSOP8 – 8-lead thin shrink small outline, package mechanical data 136 Table 130. Ordering information scheme for packaged devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 Table 131. CRC definition 139 Table 132. AFI coding 141 Table 133. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 10/143 Doc ID 018932 Rev 8 M24LR16E-R ...

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... End of frame, low data rate, one subcarrier, Fast commands . . . . . . . . . . . . . . . . . . . . . . 59 Figure 45. End of frame, high data rate, two subcarriers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Figure 46. End of frame, low data rate, two subcarriers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Figure 47. M24LR16E-R decision tree for AFI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 = 400 kHz): maximum R value versus bus parasitic bus ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Doc ID 018932 Rev 8 ...

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... List of figures Figure 48. M24LR16E-R protocol timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Figure 49. M24LR16E-R state transition diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Figure 50. Principle of comparison between the mask, the slot number and the UID . . . . . . . . . . . . . 74 Figure 51. Description of a possible anticollision sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Figure 52. M24LR16 RF-Busy management following Inventory command . . . . . . . . . . . . . . . . . . . . 82 Figure 53. Stay Quiet frame exchange between VCD and M24LR16E Figure 54 ...

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... The M24LR16E-R is organized as 2048 × 8 bits in the I 15693 and ISO 18000-3 mode 1 RF mode. The M24LR16E-R also features an energy harvesting analog output, as well as a user- configurable digital output pin toggling during either RF write in progress or RF busy mode. Figure 1. ...

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... Data are transferred from the M24LR16E-R at 6.6 Kbit/s in low data rate mode and 26 Kbit/s high data rate mode. The M24LR16E-R supports the 53 Kbit/s fast mode in high data rate mode using one subcarrier frequency at 423 kHz ...

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... This configurable output signal is used either to indicate that the M24LR16E-R is executing an internal write cycle from the RF channel or that an RF command is in progress. RF WIP and signals are available only when the M24LR16E-R is powered by the Vcc pin open drain output and a pull up resistor must be connected from RF WIP/BUSY ...

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... Supply voltage (V This pin can be connected to an external DC supply voltage. Note: An internal voltage regulator allows the external voltage applied on V M24LR16E-R, while preventing the internal power supply (rectified RF waveforms) to output a DC voltage on the V 2.7.1 Operating supply voltage V Prior to selecting the memory and issuing instructions to it, a valid and stable V ...

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... M24LR16E-R 2 Figure Fast mode (f capacitance (C 100 10 Here R bus × C bus = 120 Figure bus protocol SCL SDA SCL SDA Start Condition SCL SDA = 400 kHz): maximum bus 30 pF 100 1000 Bus line capacitor (pF) SDA SDA Start ...

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... Signal descriptions Table 2. Device select code Device select code 1. The most significant bit, b7, is sent first not connected to any external pin however used to address the M24LR16E-R as described in Section 3 and Section Table 3. Address most significant byte b15 b14 Table 4. Address least significant byte ...

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... M24LR16E-R 3 User memory organization The M24LR16E-R is divided into 16 sectors of 32 blocks of 32 bits, as shown in Figure 6 shows the memory sector organization. Each sector can be individually read- and/or write-protected using a specific password command. Read and write operations are possible if the addressed data are not in a protected sector. ...

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... Sector details The M24LR16E-R user memory is divided into 16 sectors. Each sector contains 1024 bits. The protection scheme is described mode, a sector provides 32 blocks of 32 bits. Each read and write access is done by block. Read and write block accesses are controlled by a Sector Security Status byte that defines the access rights to the 32 blocks contained in the sector ...

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... M24LR16E-R Table 5. Sector details Sector RF block number address byte Bits [31:24] address 0 0 user 1 4 user 2 8 user 3 12 user 4 16 user 5 20 user 6 24 user 7 28 user 8 32 ...

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... Doc ID 018932 Rev 8 M24LR16E-R Bits [23:16] Bits [15:8] Bits [7:0] user user user user user user user user user user user user user user user user ... ... ... ...

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... M24LR16E-R Table 5. Sector details (continued) Sector RF block number address 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 15 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511 ...

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... M24LR16E-R block security in RF mode The M24LR16E-R provides a special protection mechanism based on passwords mode, each memory sector of the M24LR16E-R can be individually protected by one out of three available passwords, and each sector can also have Read/Write access conditions set. Each memory sector of the M24LR16E-R is assigned with a Sector security status byte ...

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... Password control bits The M24LR16E-R password protection is organized around a dedicated set of commands, plus a system area of three password blocks where the password values are stored. This system area is described in Table 10. Password system area Add The dedicated commands for protection in RF mode are: ...

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... System memory area Present-sector password: The Present-sector password command is used to present one of the three passwords to the M24LR16E-R in order to modify the access rights of all the memory sectors linked to that password password is correct, the access rights remain activated until the tag is powered off or until a new Present-sector password command is issued ...

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... When bit 3 of the Configuration byte is set to 0, the RF WIP/BUSY pin is configured in RF busy mode. The purpose of this mode is to indicate to the I²C bus master whether the M24LR16E-R is busy in RF mode or not. In this mode, the RF WIP/BUSY pin is tied to 0 from the RF command Start Of Frame (SOF) until the end of the command execution ...

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... The M24LR16E-R features an Energy harvesting mode on the Vout analog output. The general purpose of the Energy harvesting mode is to deliver a part of the non- necessary RF power received by the M24LR16E-R on the AC0-AC1 RF input in order to supply an external device. The current consumption on the analog voltage output Vout is limited to ensure that the M24LR16E-R is correctly supplied during the powering of the external device ...

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... FIELD_ON indicator bit The FIELD_ON bit indicator located as Bit 1 of the Control register is a read-only bit used to indicate when the RF power level delivered to the M24LR16E-R is sufficient to execute RF commands. When FIELD_ON = 0, the M24LR16E-R is not able to execute any RF commands. When FIELD_ON =1, the M24LR16E-R is able to execute any RF commands. ...

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... Set/reset energy harvesting enable bit command (SetRstEHEn): The SetRstEHEn command is used to set or reset the value of the EH_enable bit into the Control register. 4.4 ISO 15693 system parameters The M24LR16E-R provides the system area required by the ISO 15693 RF protocol, as shown in Table 17. The first 32-bit block starting from I ...

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... M24LR16E-R The next byte stores the Configuration byte, at I²C location 2320. This Control register is used to store the three energy harvesting configuration bits and the RF WIP/BUSY configuration bit. The next two bytes are used to store the AFI location 2323. These two values are used during the RF inventory sequence. They are read- ...

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... The device that controls the data transfer is known as the bus master, and the other as the slave device. A data transfer can only be initiated by the bus master, which also provides the serial clock for synchronization. The M24LR16E-R device is a slave in all communications. ...

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... M24LR16E-R 5.5.1 I²C timeout on Start condition I²C communication with the M24LR16E-R starts with a valid Start condition, followed by a device select code. If the delay between the Start condition and the following rising edge of the Serial Clock (SCL) that samples the most significant of the Device Select exceeds the t ...

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... Start, device select ACK ACK Dev select Byte address Byte address R/W ACK ACK Dev select Byte address Byte address R/W NO ACK NO ACK Data in N Doc ID 018932 Rev 8 M24LR16E-R Initial sequence ACK NO ACK Data in ACK NO ACK Data in 1 Data in 2 AI15115 ...

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... M24LR16E-R 5.7 Write operations Following a Start condition, the bus master sends a device select code with the Read/Write bit (RW) reset to 0. The device acknowledges this, as shown in address bytes. The device responds to each address byte with an acknowledge bit, and then waits for the data byte. ...

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... YES Next operation is NO YES addressing the memory NO Data for the Write operation Continue the Write operation Doc ID 018932 Rev 8 M24LR16E-R ACK ACK ACK Data in 2 Data in N Send address and receive ACK Start YES condition Device select with Continue the ...

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... M24LR16E-R 5.10 Minimizing system delays by polling on ACK During the internal write cycle, the device disconnects itself from the bus, and writes a copy of the data from its internal latches to the memory cells. The maximum I²C write time (t shown in Table 123 can be used by the bus master. ...

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... R/W ACK ACK Dev select Data out 1 R/W ACK ACK Dev select * Byte address Byte address R/W ACK NO ACK Data out N Doc ID 018932 Rev 8 M24LR16E-R ACK ACK NO ACK Dev select * Data out R/W ACK NO ACK Data out N ACK ACK ACK Dev select * Data out 1 R/W AI01105d ...

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... M24LR16E-R 5.11 Read operations Read operations are performed independently of the state of the I2C_Write_Lock bit. After the successful completion of a read operation, the device’s internal address counter is incremented by one, to point to the next byte address. 5.12 Random Address Read A dummy write is first performed to load the address into this address counter (as shown in Figure 11) but without sending a Stop condition ...

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... A Stop condition at any other time does not trigger the internal delay. During that delay, the M24LR16E-R compares the 32 received data bits with the 32 bits of the stored I password. If the values match, the write access rights to all protected sectors are modified after the internal delay ...

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... It is necessary to send twice the 32-bit password to prevent any data corruption during the write sequence. If the two 32-bit passwords sent are not exactly the same, the M24LR16E-R does not modify the I When the bus master generates a Stop condition immediately after the Ack bit (during the tenth bit time slot), the internal write cycle is triggered ...

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... M24LR16E-R memory initial state 6 M24LR16E-R memory initial state The device is delivered with all bits in the user memory array set to 1 (each byte contains FFh). The DSFID is programmed to FFh and the AFI is programmed to 00h. Configuration byte set to F4h: Bit 7 to bit 4: all set to 1 ...

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... DSFID register in which the data storage family identifier used in the anticollision algorithm is stored. The M24LR16E-R has three 32-bit blocks in which the password codes are stored and a 8- bit Configuration byte in which the Energy harvesting mode and RF WIP/BUSY pin configuration is stored. ...

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... Commands The M24LR16E-R supports the following commands: Inventory, used to perform the anticollision sequence. Stay quiet, used to put the M24LR16E-R in quiet mode, where it does not respond to any inventory command. Select, used to select the M24LR16E-R. After this command, the M24LR16E-R processes all Read/Write commands with Select_flag set. ...

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... Power transfer Power is transferred to the M24LR16E-R by radio frequency at 13.56 MHz via coupling antennas in the M24LR16E-R and the VCD. The RF operating field of the VCD is transformed on the M24LR16E-R antenna voltage which is rectified, filtered and internally regulated. During communications, the amplitude modulation (ASK) on this received signal is demodulated by the ASK demodulator ...

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... Depending on the choice made by the VCD, a “pause” is created as described in and Figure 15. The M24LR16E-R is operational for the 100% modulation index or for any degree of modulation index between 10% and 30% (see Figure 14. 100% modulation waveform Carrier Amplitude ...

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... Modulation Modulation Modulation Index Index Index The VICC shall be operational for any value of modulation index between 10 % and 30 %. Communication signal from VCD to M24LR16E-R Parameter definition 0 – – Min Min Min ...

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... Data rate and data coding The data coding implemented in the M24LR16E-R uses pulse position modulation. Both data coding modes that are described in the ISO15693 are supported by the M24LR16E-R. The selection is made by the VCD and indicated to the M24LR16E-R within the start of frame (SOF). 9.1 Data coding mode: 1 out of 256 The value of one single byte is represented by the position of one pause ...

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... M24LR16E-R Figure 17. Detail of a time period Pulse Modulated Carrier . . 9.2 Data coding mode: 1 out of 4 The value of two bits is represented by the position of one pause. The position of the pause successive time periods of 18.88 µs (256/f Four successive pairs of bits form a byte, where the least significant pair of bits is transmitted first. In this case, the transmission of one byte takes 302.08 µ ...

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... Pulse position for "01" (1=LSB) Pulse position for "10" (0=LSB) Pulse position for "11" Figure 19. 1 out of 4 coding example 10 75.52µs 50/143 75.52 µs 28.32 µs 9.44 µs 75.52 µs 47.20µs 75.52 µs 75.52 µs 00 75.52µs 75.52µs Doc ID 018932 Rev 8 M24LR16E-R 9.44 µs 66.08 µs 9.44 µs AI06658 01 11 75.52µs AI06659 ...

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... The M24LR16E-R is ready to receive a new command frame from the VCD 311.5 µs (t after sending a response frame to the VCD. The M24LR16E-R takes a power-up time of 0.1 ms after being activated by the powering field. After this delay, the M24LR16E-R is ready to receive a command frame from the VCD. 9.4 Start of frame (SOF) The SOF defines the data coding mode the VCD is to use for the following command frame ...

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... Data rate and data coding Figure 22. EOF for either data coding mode 52/143 9.44µs 9.44µs 37.76µs Doc ID 018932 Rev 8 M24LR16E-R AI06662 ...

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... Data rates The M24LR16E-R can respond using the low or the high data rate format. The selection of the data rate is made by the VCD using the second bit in the protocol header. For fast commands, the selected data rate is multiplied by two. ...

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... For the Fast commands, a logic 1 starts with an unmodulated time of 9.44 µs followed by four pulses of 423.75 kHz (f Figure 26. Logic 1, high data rate, fast commands 54/143 C Figure 23. 37.76µs Figure 24. 18.88µs Figure 25. 37.76µs /32), as shown in Figure C 18.88µs Doc ID 018932 Rev 8 M24LR16E-R /32) followed by an unmodulated time of ai12076 /32) followed ai12066 ai12077 26. ai12067 ...

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... M24LR16E-R 11.1.2 Low data rate A logic 0 starts with 32 pulses at 423.75 kHz (f 75.52 µs, as shown in Figure 27. Logic 0, low data rate For the Fast commands, a logic 0 starts with 16 pulses at 423.75 kHz (f unmodulated time of 37.76 µs, as shown in Figure 28. Logic 0, low data rate, fast commands A logic 1 starts with an unmodulated time of 75.52 µs followed by 32 pulses at 423.75 kHz ...

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... Bit coding using two subcarriers is not supported for the Fast 149.84µs /28) followed by 32 pulses at 423.75 kHz C Figure 34. Bit coding using two subcarriers is not supported for the Fast 149.84µs Doc ID 018932 Rev 8 M24LR16E-R /32) followed by nine pulses at ai12074 /28) followed by eight pulses at ai12073 ai12072 ai12075 ...

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... Figure 37. Start of frame, low data rate, one subcarrier Figure 35. 113.28µs /32), and a logic 1 that consists of an unmodulated time of C 56.64µs Figure 37. 453.12µs Doc ID 018932 Rev 8 M24LR16E-R to VCD frames 37.76µs ai12078 Figure 36. 18.88µs ai12079 151.04µs ai12080 57/143 ...

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... M24LR16E-R to VCD frames For the Fast commands, the SOF comprises an unmodulated time of 113.28 µs, followed by 48 pulses at 423.75 kHz (f followed by 16 pulses at 423.75 kHz, as shown in Figure 38. Start of frame, low data rate, one subcarrier, fast commands 12.2 SOF when using two subcarriers 12.2.1 High data rate The SOF comprises 27 pulses at 484 ...

Page 59

... Figure 44. End of frame, low data rate, one subcarrier, Fast commands Figure 41. 56.64µs 18.88µs Figure 43. Figure 44. 75.52µs 226.56µs Doc ID 018932 Rev 8 M24LR16E-R to VCD frames /32), and by an unmodulated time C 113.28µs ai12084 Figure 42. ai12085 /32) and an unmodulated time of C 453.12µs ai12086 /32) and an ...

Page 60

... M24LR16E-R to VCD frames 12.4 EOF when using two subcarriers 12.4.1 High data rate The EOF comprises a logic 0 that includes eight pulses at 423.75 kHz and nine pulses at 484.28 kHz, followed by 24 pulses at 423.75 kHz (f (f /28), as shown in C Bit coding using two subcarriers is not supported for the Fast commands. ...

Page 61

... IC manufacturer code “ST 02h” bits (ISO/IEC 7816-6/AM1), a unique serial number on 48 bits. Table 21. UID format 63 0xE0 With the UID, each M24LR16E-R can be addressed uniquely and individually during the anticollision loop and for one-to-one exchanges between a VCD and an M24LR16E-R. MSB ...

Page 62

... Figure 47. M24LR16E-R decision tree for AFI The AFI is programmed by the M24LR16E-R issuer (or purchaser) in the AFI register. Once programmed and locked, it can no longer be modified. The most significant nibble of the AFI is used to code one specific or all application families. ...

Page 63

... EOF. The CRC is calculated on all the bytes after the SOF up to the CRC field. Upon reception of a request from the VCD, the M24LR16E-R verifies that the CRC value is valid invalid, the M24LR16E-R discards the frame and does not answer to the VCD. Upon reception of a response from the M24LR16E- recommended that the VCD verifies whether the CRC value is valid ...

Page 64

... VCD and the M24LR16E-R in both directions based on the concept of “VCD talks first”. This means that an M24LR16E-R does not start transmitting unless it has received and properly decoded an instruction sent by the VCD. The protocol is based on an exchange of: a request from the VCD to the M24LR16E-R, a response from the M24LR16E-R to the VCD ...

Page 65

... M24LR16E-R Figure 48. M24LR16E-R protocol timing Request VCD (Table M24LR16 E-R Timing frame 23) Response frame (Table 24) <-t -> <-t 1 Doc ID 018932 Rev 8 M24LR16E-R protocol description Request frame (Table 23) Response frame (Table -> <-t -> 24) <-t -> 2 65/143 ...

Page 66

... Quiet Selected Transitions between these states are specified in 17.1 Power-off state The M24LR16E the Power-off state when it does not receive enough energy from the VCD. 17.2 Ready state The M24LR16E the Ready state when it receives enough energy from the VCD. When in the Ready state, the M24LR16E-R answers any request where the Select_flag is not set ...

Page 67

... Address_Flag is set AND where Inventory_Flag is not set 1. The M24LR16E-R returns to the Power Off state if the tag is out of the RF field for at least t refer to application note AN4125 for more information. 2. The intention of the state transition method is that only one M24LR16E-R should be in the Selected state at a time ...

Page 68

... M24LR16E-R. Any M24LR16E-R that receives a request with the Address_flag set to 1 compares the received Unique ID to its own matches, then the M24LR16E-R executes the request (if possible) and returns a response to the VCD as specified in the command description. If the UID does not match, then it remains silent. ...

Page 69

... The flags field consists of eight bits. Bit 3 (Inventory_flag) of the request flag defines the contents of the four MSBs (bits 5 to 8). When bit 3 is reset (0), bits define the M24LR16E-R selection criteria. When bit 3 is set (1), bits define the M24LR16E-R Inventory parameters. ...

Page 70

... AFI flag Bit 6 Nb_slots flag Bit 7 Option flag Bit 8 RFU 70/143 Level Request is executed by any M24LR16E-R according to the setting 0 of Address_flag (1) 1 Request is executed only by the M24LR16E-R in Selected state Request is not addressed. UID field is not present. The request is 0 executed by all M24LR16E-Rs. ...

Page 71

... General response format S O Response_flags F 20.1 Response flags In a response, the flags indicate how actions have been performed by the M24LR16E-R and whether corresponding fields are present or not. The response flags consist of eight bits. Table 31. Definitions of response flags Bit No Bit 1 Error_flag Bit 2 ...

Page 72

... Response format 20.2 Response error code If the Error_flag is set by the M24LR16E-R in the response, the Error code field is present and provides information about the error that occurred. Error codes not specified in Table 32. Response error code definition Error code 03h 0Fh 10h 11h 12h ...

Page 73

... M24LR16E-R 21 Anticollision The purpose of the anticollision sequence is to inventory the M24LR16E-Rs present in the VCD field using their unique ID (UID). The VCD is the master of communications with one or several M24LR16E-Rs. It initiates M24LR16E-R communication by issuing the Inventory request. The M24LR16E-R sends its response in the determined slot or does not respond. ...

Page 74

... The first slot starts immediately after the request EOF is received. To switch to the next slot, the VCD sends an EOF. The following rules and restrictions apply M24LR16E-R answer is detected, the VCD may switch to the next slot by sending an EOF. If one or more M24LR16E-R answers are detected, the VCD waits until the complete frame has been received before sending an EOF for switching to the next slot ...

Page 75

... M24LR16E-R 22 Request processing by the M24LR16E-R Upon reception of a valid request, the M24LR16E-R performs the following algorithm: NbS is the total number of slots ( the current slot number (0 to 15) LSB (value, n) function returns the n Less Significant Bits of value MSB (value, n) function returns the n Most Significant Bits of value “ ...

Page 76

... The VCD sends an Inventory request frame terminated by an EOF. The number of slots is 16. M24LR16E-R_1 transmits its response in Slot the only one to do so, therefore no collision occurs and its UID is received and registered by the VCD. The VCD sends an EOF in order to switch to the next slot. ...

Page 77

Slot 0 Inventory VCD SOF EOF EOF Request Response M24RF64s Response Response 1 Timing Comment Collision collision Time Slot 1 Slot 2 Slot 3 Request to EOF EOF SOF M24RF64_1 Response 2 4 Response 3 5 ...

Page 78

... Inventory Initiated command 24 Inventory Initiated command The M24LR16E-R provides a special feature to improve the inventory time response of moving tags using the Initiate_flag value. This flag, controlled by the Initiate command, allows tags to answer to Inventory Initiated commands. For applications in which multiple tags are moving in front of a reader possible to miss tags using the standard inventory command ...

Page 79

... EOF from the M24LR16E-Rs. The EOF sent by the VCD may be either 10% or 100% modulated regardless of the modulation index used for transmitting the VCD request to the M24LR16E- also the time after which the VCD may send a new request to the M24LR16E- described in Figure ...

Page 80

... Command codes 26 Command codes The M24LR16E-R supports the commands described in this section. Their codes are given in Table 36. Table 36. Command codes Command code standard 01h 02h 20h 21h 23h 25h 26h 27h 28h 29h 2Ah 2Bh 80/143 Function Inventory Stay Quiet Read Single Block ...

Page 81

... Inventory response format Response Response_ SOF flags 8 bits During an Inventory process, if the VCD does not receive an RF M24LR16E-R response, it waits for a time t 3 edge of the request EOF sent by the VCD. If the VCD sends a 100% modulated EOF, the minimum value min = 4384/f ...

Page 82

... Slot Inventory Slot Inventory O O command F F Slot Inventory O O command F F Doc ID 018932 Rev 8 M24LR16E-R Slot Ireply O M24LR16 F Power-off Slot INew Ireply command M24LR16 F ...

Page 83

... M24LR16E-R 26.2 Stay Quiet Command code = 0x02 On receiving the Stay Quiet command, the M24LR16E-R enters the Quiet State if no error occurs, and does NOT send back a response. There is NO response to the Stay Quiet command even if an error occurs. When in the Quiet state: the M24LR16E-R does not process any request if the Inventory_flag is set, the M24LR16E-R processes any Addressed request ...

Page 84

... On receiving the Read Single Block command, the M24LR16E-R reads the requested block and sends back its 32-bit value in the response. The Protocol_extension_flag should be set to 1 for the M24LR16E-R to operate correctly. If the Protocol_extension_flag the M24LR16E-R answers with an error code. The Option_flag is supported. ...

Page 85

... The Protocol_extension_flag should be set to 1 for the M24LR16E-R to operate correctly. If the Protocol_extension_flag the M24LR16E-R answers with an error code. The Option_flag is supported. During the RF write cycle W otherwise, the M24LR16E-R may not program correctly the data into the memory. The W time is equal to t 1nom Table 44. ...

Page 86

... R When configured in the RF busy mode, the RF WIP/BUSY pin is tied to 0 from the SOF that starts the Write Single Block command to the end of the M24LR16E-R response. When configured in the RF write in progress mode, the RF WIP/BUSY pin is tied to 0 for the duration of the internal write cycle (from the end of a valid write single block command to the beginning of the M24LR16E-R response) ...

Page 87

... M24LR16E-R Figure 56. M24LR16 RF-Busy management following Write command 1) M24LR16 replies. RF_Busy is released after M24LR16 response command F RF_Busy 2) M24LR16 replies when option flag is set. RF_Busy is released after M24LR16 response command F RF_Busy 3) VCD sends a forbidden Write (sector lock, password-protected). RF_Busy is released after M24LR16 command. ...

Page 88

... VCD sends a forbidden Write (sector lock, password-protected). RF_Wip is released after M24LR16 command command F RF_Wip 88/143 Wt E Write Write Write O F Doc ID 018932 Rev 8 M24LR16E-R Figure 57 Ireply O O M24LR16 Ireply M24LR16 Ireply O ...

Page 89

... If the number of blocks overlaps sectors, the M24LR16E-R returns an error code. The Protocol_extension_flag should be set to 1 for the M24LR16E-R to operate correctly. If the Protocol_extension_flag the M24LR16E-R answers with an error code. The Option_flag is supported ...

Page 90

... If the UID does not match its own, the selected M24LR16E-R returns to the Ready state and does not send a response. The M24LR16E-R answers an error code only if the UID is equal to its own UID. If not, no response is generated error occurs, the M24LR16E-R remains in its current state. ...

Page 91

... Figure 59. Select frame exchange between VCD and M24LR16E-R VCD M24LR16E-R When configured in the RF busy mode, the RF WIP/BUSY pin is tied to 0 from the SOF that starts the Select command to the end of the M24LR16E-R response. When configured in the RF write in progress mode, the RF WIP/BUSY pin remains in high-Z state. 8 bits ...

Page 92

... Command codes 26.7 Reset to Ready On receiving a Reset to Ready command, the M24LR16E-R returns to the Ready state if no error occurs. In the Addressed mode, the M24LR16E-R answers an error code only if the UID is equal to its own UID. If not, no response is generated. Table 54. Reset to Ready request format Request ...

Page 93

... On receiving the Write AFI request, the M24LR16E-R programs the 8-bit AFI value to its memory. The Option_flag is supported. During the RF write cycle W otherwise, the M24LR16E-R may not write correctly the AFI value into the memory. The W time is equal to t 1nom Table 57. ...

Page 94

... Lock AFI On receiving the Lock AFI request, the M24LR16E-R locks the AFI value permanently. The Option_flag is supported. During the RF write cycle W otherwise, the M24LR16E-R may not Lock correctly the AFI value in memory. The W equal × 302 µs. 1nom Table 60. ...

Page 95

... M24LR16E-R When configured in the RF busy mode, the RF WIP/BUSY pin is tied to 0 from the SOF that starts the Lock AFI command to the end of the M24LR16E-R response. When configured in the RF write in progress mode, the RF WIP/BUSY pin is tied to 0 for the entire duration of the internal write cycle (from the end of valid Lock AFI command to the beginning of the M24LR16E-R response) ...

Page 96

... Command codes 26.10 Write DSFID On receiving the Write DSFID request, the M24LR16E-R programs the 8-bit DSFID value to its memory. The Option_flag is supported. During the RF write cycle W otherwise, the M24LR16E-R may not write correctly the DSFID value in memory. The W time is equal to t 1nom Table 63 ...

Page 97

... Lock DSFID On receiving the Lock DSFID request, the M24LR16E-R locks the DSFID value permanently. The Option_flag is supported. During the RF write cycle W otherwise, the M24LR16E-R may not lock correctly the DSFID value in memory. The W is equal × 302 µs. 1nom Table 66. ...

Page 98

... M24LR16E-R When configured in the RF busy mode, the RF WIP/BUSY pin is tied to 0 from the SOF that starts the Lock DSFID command to the end of the M24LR16E-R response. When configured in the RF write in progress mode, the RF WIP/BUSY pin is tied to 0 for the duration of the internal write cycle (from the end of a valid Lock DSFID command to the beginning of the M24LR16E-R response) ...

Page 99

... M24LR16E-R 26.12 Get System Info When receiving the Get System Info command, the M24LR16E-R sends back its information data in the response.The Option_flag is not supported. The Get System Info can be issued in both Addressed and Non Addressed modes. The Protocol_extension_flag can be set ...

Page 100

... Figure 65. Get System Info frame exchange between VCD and M24LR16E-R VCD M24LR16E-R When configured in the RF busy mode, the RF WIP/BUSY pin is tied to 0 from the SOF that starts the Get System Info command to the end of the M24LR16E-R response. When configured in the RF write in progress mode, the RF WIP/BUSY pin remains in high-Z state. 100/143 ...

Page 101

... For example, a value of '06' in the “Number of blocks” field requests to return the security status of seven blocks. The Protocol_extension_flag should be set to 1 for the M24LR16E-R to operate correctly. If the Protocol_extension_flag the M24LR16E-R answers with an error code. ...

Page 102

... VCD M24LR16E-R When configured in the RF busy mode, the RF WIP/BUSY pin is tied to 0 from the SOF that starts the Get Multiple Block Security Status command to the end of the M24LR16E-R response. When configured in the RF write in progress mode, the RF WIP/BUSY pin remains in high-Z state. ...

Page 103

... Figure 67. Write-sector Password frame exchange between VCD and M24LR16E-R VCD M24LR16E-R M24LR16E-R Response_flags 8 bits Error code ...

Page 104

... Care must be taken when issuing the Lock- sector command as all the blocks belonging to the same sector are automatically locked by a single command. The Protocol_extension_flag should be set to 1 for the M24LR16E-R to operate correctly. If the Protocol_extension_flag the M24LR16E-R answers with an error code. During the RF write cycle W otherwise, the M24LR16E-R may not correctly lock the memory block ...

Page 105

... The Option_flag is supported. During the comparison cycle equal to W 10%), otherwise, the M24LR16E-R the Password value may not be correctly compared. The W time is equal ...

Page 106

... Present- IC Password (1) sector Mfg UID number Password code B3h 02h 64 bits 8 bits 8 bits Error code 8 bits Doc ID 018932 Rev 8 M24LR16E-R Password CRC16 32 bits 16 bits Response CRC16 EOF 16 bits Response CRC16 16 bits Request EOF EOF ...

Page 107

... SOF M24LR16E-R M24LR16E-R When configured in the RF busy mode, the RF WIP/BUSY pin is tied to 0 from the SOF that starts the Present Sector Password command to the end of the M24LR16E-R response. When configured in the RF write in progress mode, the RF WIP/BUSY remains in high-Z state. Present- sector ...

Page 108

... The Protocol_extension_flag should be set to 1 for the M24LR16E-R to operate correctly. If the Protocol_extension_flag the M24LR16E-R answers with an error code. The subcarrier_flag should be set to 0, otherwise the M24LR16E-R answers with an error code. Table 87. Fast Read Single Block request format ...

Page 109

... Figure 70. Fast Read Single Block frame exchange between VCD and M24LR16E-R VCD M24LR16E-R When configured in the RF busy mode, the RF WIP/BUSY pin is tied to 0 from the SOF that starts the Fast Read Single block command to the end of the M24LR16E-R response. When configured in the RF write in progress mode, the RF WIP/BUSY pin remains in high-Z state. 26.18 ...

Page 110

... Fast Inventory Initiated response format Response Response SOF _flags 8 bits During an Inventory process, if the VCD does not receive an RF M24LR16E-R response, it waits for a time t 3 edge of the request EOF sent by the VCD. If the VCD sends a 100% modulated EOF, the minimum value ...

Page 111

... Non Addressed mode only (Select_flag is reset to 0 and Address_flag is reset to 0 error occurs, the M24LR16E-R does not generate any answer. The Initiate_flag is reset after a power-off of the M24LR16E-R. The data rate of the response is multiplied by 2. The subcarrier_flag should be set to 0, otherwise the M24LR16E-R answers with an error code ...

Page 112

... The Protocol_extension_flag should be set to 1 for the M24LR16E-R to operate correctly. If the Protocol_extension_flag the M24LR16E-R answers with an error code. The Option_flag is supported. The data rate of the response is multiplied by 2. The subcarrier_flag should be set to 0, otherwise the M24LR16E-R answers with an error code. Table 95. ...

Page 113

... Inventory Initiated Before receiving the Inventory Initiated command, the M24LR16E-R must have received an Initiate or a Fast Initiate command in order to set the Initiate_ flag. If not, the M24LR16E-R does not answer to the Inventory Initiated command. On receiving the Inventory Initiated request, the M24LR16E-R runs the anticollision sequence ...

Page 114

... Table 100. Inventory Initiated response format Response Response SOF _flags 8 bits During an Inventory process, if the VCD does not receive an RF M24LR16E-R response, it waits for a time t 3 edge of the request EOF sent by the VCD. If the VCD sends a 100% modulated EOF, the minimum value ...

Page 115

... The command has to be issued in the Non Addressed mode only (Select_flag is reset to 0 and Address_flag is reset to 0 error occurs, the M24LR16E-R does not generate any answer. The Initiate_flag is reset after a power-off of the M24LR16E-R. ...

Page 116

... On receiving the ReadCfg command, the M24LR16E-R reads the Configuration byte and sends back its 8-bit value in the response. The Protocol_extension_flag should be set to 0 for the M24LR16E-R to operate correctly. If the Protocol_extension_flag the M24LR16E-R answers with an error code. The Option_flag is not supported. The Inventory_flag must be set to 0. ...

Page 117

... On receiving the WriteEHCfg command, the M24LR16E-R writes the data contained in the request to the Configuration byte and reports whether the write operation was successful in the response. The Protocol_extension_flag should be set to 0 for the M24LR16E-R to operate correctly. If the Protocol_extension_flag the M24LR16E-R answers with an error code. The Option_flag is supported, the Inventory_flag is not supported. ...

Page 118

... M24LR16E-R response). 26.25 WriteDOCfg On receiving the WriteDOCfg command, the M24LR16E-R writes the data contained in the request to the Configuration byte and reports whether the write operation was successful in the response. The Protocol_extension_flag should be set to 0 for the M24LR16E-R to operate correctly. If the Protocol_extension_flag the M24LR16E-R answers with an error code ...

Page 119

... M24LR16E-R When configured in the RF busy mode, the RF WIP/BUSY pin is tied to 0 from the SOF that starts the WriteEHCfg command to the end of the M24LR16E-R response. When configured in the RF write in progress mode, the RF WIP/BUSY pin is tied to 0 for the entire duration of the internal write cycle (from the end of a valid WriteDOCfg command to the beginning of the M24LR16E-R response) ...

Page 120

... Command codes 26.26 SetRstEHEn On receiving the SetRstEHEn command, the M24LR16E-R sets or resets the EH_enable bit in the volatile Control register. The Protocol_extension_flag should be set to 0 for the M24LR16E-R to operate correctly. If the Protocol_extension_flag the M24LR16E-R answers with an error code. The Option_flag and the Inventory_flag are not supported. ...

Page 121

... On receiving the CheckEHEn command, the M24LR16E-R reads the Control register and sends back its 8-bit value in the response. The Protocol_extension_flag should be set to 0 for the M24LR16E-R to operate correctly. If the Protocol_extension_flag the M24LR16E-R answers with an error code. The Option_flag is not supported. The Inventory_flag must be set to 0. ...

Page 122

... Figure 78. CheckEHEn frame exchange between VCD and M24LR16E-R VCD M24LR16E-R When configured in the RF busy mode, the RF WIP/BUSY pin is tied to 0 from the SOF that starts the CheckEHEn command to the end of the M24LR16E-R response. When configured in the RF write in progress mode, the RF WIP/BUSY pin remains in high-Z state. 122/143 ...

Page 123

... M24LR16E-R 27 Maximum rating Stressing the device above the rating listed in the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect the device reliability ...

Page 124

... Pulse width ignored (Input filter on SCL and SDA Characterized only. 124/143 2 C mode. The parameters in the DC and AC characteristic Parameter Parameter Input Levels Timing Reference Levels 0.8V CC 0.2V CC Parameter Doc ID 018932 Rev 8 M24LR16E-R Min. Max. Unit 1.8 5.5 V –40 85 °C Min. Max. Unit 100 ...

Page 125

... M24LR16E-R 2 Table 122 characteristics Symbol Input leakage current I LI (SCL, SDA) Vout output leakage I LO_Vout current I Output leakage current LO I Supply current (Read Supply current (Write) CC0 I Standby supply current CC1 Input low voltage (SDA SCL) Input high voltage (SDA, ...

Page 126

... Clock low to next data valid (access time) Start condition set up time Start condition hold time Stop condition set up time Time between Stop condition and next Start condition I²C write time 2 C specification (which specifies t Figure Doc ID 018932 Rev 8 M24LR16E-R Table 119 Min. Max. 25 400 0.6 20000 1.3 20000 40 ...

Page 127

... M24LR16E-R 2 Figure 80 waveforms tXL1XL2 tXH1XH2 SCL tDLCL SDA In tCHDX tXH1XH2 Start condition SCL SDA In tCHDH Stop condition SCL tCLQV SDA Out tCHCL tCLCH tCLDX tDXCX SDA Change SDA Input tW Write cycle tCHCL tCLQX Data valid Data valid Doc ID 018932 Rev 8 ...

Page 128

... RFSBL Minimum time from carrier t MIN CD generation to first data f Subcarrier frequency high SH f Subcarrier frequency low SL t Time for M24LR16E-R response 1 t Time between commands 2 RF write time (including internal W t Verify) I Operating current (Read) CC_RF C ...

Page 129

... Symbol T Ambient operating temperature A Figure 81 shows an ASK modulated signal from the VCD to the M24LR16E-R. The test condition for the AC/DC parameters are: Close coupling condition with tester antenna (1 mm) M24LR16E-R performance measured at the tag antenna M24LR16E-R synchronous timing, transmit and receive (1) (2) ...

Page 130

... Vout for the various Energy (1) (2) (3) (4) P Vout@I=0 min 2.7 V min 100 mW 4.5 V max 2.7 V min 66 mW 4.5 V max 2.7 V min 33 mW 4.5 V max 2.7 V min 18 mW 4.5 V max Doc ID 018932 Rev 8 M24LR16E-R t RFR f CC MS19784V1 Vout@I I sink_max sink_max 2.3 V 300 µA AC0- @P min ...

Page 131

... M24LR16E-R Figure 82. Vout min vs. Isink Figure 83. Range 11 domain Field (H) 3.5 A/m 2.4 A/m 1.3 A/m 0.8 A/m 300 μ Doc ID 018932 Rev 8 RF electrical parameters MS19777V1 Output current 6 mA MS19758V1 131/143 ...

Page 132

... RF electrical parameters Figure 84. Range 10 domain Field (H) 3.5 A/m 2.4 A/m 1.3 A/m 0.8 A/m Figure 85. Range 01 domain Field (H) 3.5 A/m 2.4 A/m 1.3 A/m 0.8 A/m 132/143 300 μ 300 μ Doc ID 018932 Rev 8 M24LR16E-R Output current 6 mA MS19759V1 Output current 6 mA MS19760V1 ...

Page 133

... M24LR16E-R Figure 86. Range 00 domain Field (H) 3.5 A/m 2.4 A/m 1.3 A/m 0.8 A/m 300 μ Doc ID 018932 Rev 8 RF electrical parameters Output current 6 mA MS19761V1 133/143 ...

Page 134

... Typ Min Max 1.75 0.10 0.25 1.25 0.28 0.48 0.17 0.23 0.10 4.90 4.80 5.00 6.00 5.80 6.20 3.90 3.80 4.00 1.27 – – 0.25 0.50 0° 8° 0.40 1.27 1.04 Doc ID 018932 Rev 8 M24LR16E 45˚ c 0.25 mm GAUGE PLANE SO-A (1) inches Typ Min 0.0039 0.0492 0.0110 0.0067 0.1929 0.1890 0.2362 0.2283 0.1535 0.1496 0.0500 – 0° 0.0157 0.0410 ® Max 0.0689 0.0098 ...

Page 135

... M24LR16E-R Figure 88. UFDFPN8 (MLP8) – 8-lead ultra thin fine pitch dual flat package no lead 2 × 3mm, package outline Drawing is not to scale. 2. The central pad (E2 × D2 area in the above illustration) is internally pulled connected to any other voltage or signal line on the PCB, for example during the soldering process. ...

Page 136

... Typ Min Max 1.2 0.05 0.15 1 0.8 1.05 0.19 0.3 0.09 0.2 0.1 3 2.9 3.1 0. 6.4 6.2 6.6 4.4 4.3 4.5 0.6 0.45 0.75 1 0° 8° 8 Doc ID 018932 Rev 8 M24LR16E TSSOP8AM inches (1) Typ Min Max 0.0472 0.002 0.0059 0.0394 0.0315 0.0413 0.0075 0.0118 0.0035 0.0079 0.0039 0.1181 0.1142 0.122 0.0256 - - 0.252 0.2441 0.2598 0.1732 0.1693 0.1772 0.0236 ...

Page 137

... E = support for energy harvesting Operating voltage 1 Package MN = SO8N (150 mils width UFDFPN8 (MLP8 TSSOP8 Device grade 6 = industrial: device tested with standard test flow over – °C Option T = Tape and reel packing Capacitance /2 = 27.5 pF M24LR16E-R MN Doc ID 018932 Rev 8 Part numbering 137/143 ...

Page 138

... M24LR16E-R is inventoried then store (M24LR16E-R_UID) else ; remember a collision was detected push(mask,address) endif next sub_address if stack_not_empty ...

Page 139

... CRC (informative) B.1 CRC error detection method The cyclic redundancy check (CRC) is calculated on all data contained in a message, from the start of the flags through to the end of Data. The CRC is used from VCD to M24LR16E- R and from M24LR16E-R to VCD. Table 131. CRC definition CRC type ...

Page 140

... LSByte, then MSByte) } else // check CRC { if (current_crc_value == CHECK_VALUE) { printf ("Checked CRC is ok (0x%04X)\n", current_crc_value); } else { printf ("Checked CRC is NOT ok (0x%04X)\n", current_crc_value 140/143 current_crc_value = (current_crc_value >> current_crc_value = (current_crc_value >> 1); Doc ID 018932 Rev 8 M24LR16E-R ...

Page 141

... Application family identifier (AF (informative) The AFI (application family identifier) represents the type of application targeted by the VCD and is used to extract from all the M24LR16E-Rs present only the M24LR16E-R meeting the required application criteria programmed by the M24LR16E-R issuer (the purchaser of the M24LR16E-R). Once locked, it cannot be modified ...

Page 142

... Figure 86: Range 00 domain Modified Table 10: Password system area on page 25 column). 7 Modified Table 126: Energy harvesting on page 130 instead of 4.0 V max). Updated Table 5: Sector details on page 21 M24LR16E-R state transition 8 Updated clock pulse width values in on page 126. Doc ID 018932 Rev 8 M24LR16E-R Changes ratings 86. (Removed “ ...

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