M24LR16E-RDW6T/2 STMicroelectronics, M24LR16E-RDW6T/2 Datasheet - Page 35

• Manufacturer Part Number: M24LR16E-RDW6T/2
• Description: EEPROM 16kB EEPROM Dual INT 400 kHz IC2 13.56MHz
• Manufacturer: STMicroelectronics

Specifications of M24LR16E-RDW6T/2

• Product Category: EEPROM
• Rohs: yes
• Memory Size: 16 Kbit
• Organization: 256 x 8
• Data Retention: 40 yr
• Maximum Clock Frequency: 400 KHz
• Maximum Operating Current: 50 mA
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: TSSOP-8
• Access Time: 900 ns
• Interface Type: 2-Wire Serial, I2C
• Minimum Operating Temperature: -40 C
• Operating Current: 50 mA

M24LR16E-R
5.7
5.8
5.9
Write operations
Following a Start condition, the bus master sends a device select code with the Read/Write
bit (RW) reset to 0. The device acknowledges this, as shown in
address bytes. The device responds to each address byte with an acknowledge bit, and
then waits for the data byte.
Writing to the memory may be inhibited if the I2C_Write_Lock bit = 1. A Write instruction
issued with the I2C_Write_Lock bit = 1 and with no I2C_Password presented does not
modify the memory contents, and the accompanying data bytes are not acknowledged, as
shown in
Each data byte in the memory has a 16-bit (two byte wide) address. The most significant
byte
the address of the byte in memory.
When the bus master generates a Stop condition immediately after the Ack bit (in the tenth-
bit time slot), either at the end of a byte write or a page write, the internal write cycle is
triggered. A Stop condition at any other time slot does not trigger the internal write cycle.
After the Stop condition, the delay t
the device’s internal address counter is incremented automatically, to point to the next byte
address after the last one that was modified.
During the internal write cycle, the serial data (SDA) signal is disabled internally, and the
device does not respond to any requests.
Byte write
After the device select code and the address bytes, the bus master sends one data byte. If
the addressed location is write-protected by the I2C_Write_Lock bit (= 1), the device replies
with NoAck, and the location is not modified. If the addressed location is not write-protected,
the device replies with Ack. The bus master terminates the transfer by generating a Stop
condition, as shown in
Page write
The Page write mode allows up to four bytes to be written in a single write cycle, provided
that they are all located in the same “row” in the memory: that is, the most significant
memory address bits (b12-b2) are the same. If more bytes are sent than fit up to the end of
the row, a condition known as “roll-over” occurs. This should be avoided, as data starts to
become overwritten in an implementation-dependent way.
The bus master sends from one to four bytes of data, each of which is acknowledged by the
device if the I2C_Write_Lock bit = 0 or the I2C_Password was correctly presented. If the
I2C_Write_Lock_bit = 1 and the I2C_password are not presented, the contents of the
addressed memory location are not modified, and each data byte is followed by a NoAck.
After each byte is transferred, the internal byte address counter (inside the page) is
incremented. The transfer is terminated by the bus master generating a Stop condition.
(Table
Figure
3) is sent first, followed by the least significant byte
8.
Figure
Doc ID 018932 Rev 8
9.
W
, and the successful completion of a Write operation,
(Table
Figure
4). Bits b15 to b0 form
I
2
8, and waits for two
C device operation
35/143